library ieee;
use ieee.std_logic_1164.all;

entity flipflop is
	port (
		d : in std_logic;
		e : in std_logic;
		q : out std_logic;
		q_n : out std_logic
	);
end entity;

architecture rtl of flipflop is
	signal state : std_logic;
begin
	store: process(e)
	begin
		if rising_edge(e) then
			state <= d;
		end if;
	end process;

	q <= state;
	q_n <= not state;
end architecture;