dipl/sections/DP/PARALLELBUS/main.tex

\subsection{Parallel bus}

The core part of the hardware is the interface between the microprocessor and
the hardware peripherials. This bus is delivering data in parallel and is
therefore named the ``parallel bus``.  This bus has 3 different sub-parts:

\begin{enumerate}
	\item{The address bus}
	\item{The data bus}
	\item{The control bus}
\end{enumerate}

This split is common in many computer architectures and bus systems used by
various microprocessor manufacturers. In figure \ref{fig:atari_pbi} the
layout of the Atari Parallel Bus Interface is shown as used on the Atari 800XL.

\begin{figure}[H]
	\includegraphics[width=\textwidth, angle=0]{pics/atari_pbi}
	\caption{Atari PBI Pinout;Source: \url{https://www.atarimagazines.com}}
	\label{fig:atari_pbi}
\end{figure}

\subsubsection{Address Bus}

The address bus contains the nescessary data lines for addressing the individual
registers of the Serial connection and the UART. On any modern system this bus
is from 16 to 64 bits wide. For our implementation the bus size was chosen to
be 8 bit, which is multiple times the amount of needed address space, but 
is the smallest addressable unit on most microcontroller architectures and
therefore easy to program with. The address bus is unidirectional.

\subsection{Data Bus}

The data bus contains the actual data to be stored to and read from registers.
The data bus is, as well on most systems a multiple of 16 bits wide, but for the
same reasons as the data bus, was shrunk down in our case to 8 bits. The data
bus is bidirectional.

\subsection{Control Bus}

Control bus is a term which referes to any control lines (such as read and write
lines or clock lines)  which are neither address nor data bus. The control bus
in our case is 5 bits wide and consists of:

\begin{itemize}
	\item{$MR$ ... Master Reset}
	\item{$\lnot WR$ ... Write Not}
	\item{$\lnot RD$ ... Read Not}
	\item{$\lnot MS1$ ... Module Select 1 Not}
	\item{$\lnot MS2$ ... Module Select 2 Not}
\end{itemize}

\subsubsection{Master Reset}

A high level on the $MR$ lane signals to the peripherials that a reset of all
registers and states should occure. This is needed for the serial console and
the DAC.

\subsubsection{Write Not}
A low level on the $\lnot WR$ lane signals the corresponding modules that the 
data on
the data bus should be written to the register on the address specified from the
address bus.

\subsubsection{Read Not}
A low level on the $\lnot RD$ lane signals the corresponding modules that the 
data
from the register specified by the address on the address bus should be written
to the data bus.

\subsubsection{Module Select 1 and 2 Not}

A low level on one of these lines signals the corresponding module that the
data on address data and the control lines is meant for it.