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Re-added main.pdf... armin man. why? I use lfs for that

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Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
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Tyrolyean 2020-03-27 18:40:13 +01:00
parent af6338dbd3
commit 647284c492
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GPG key ID: 81EC9BAC5E9667C6
22 changed files with 1300 additions and 386 deletions
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1
.gitignore vendored
View file

@ -15,7 +15,6 @@
*.run.xml
*.synctex.gz
*.dvi
*.pdf
*.xdv
*.out
*.kate-swp

61
main.aux
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@ -262,8 +262,8 @@
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\abx@aux@segm{0}{0}{nextpnr-xilinx}
\abx@aux@cite{prjxray}
@ -313,7 +313,62 @@
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342
main.bbl
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@ -369,6 +369,348 @@
\verb https://www.nongnu.org/avr-libc/user-manual/pgmspace.html
\endverb
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\verb https://github.com/YosysHQ/yosys
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\verb{urlraw}
\verb https://github.com/tgingold/ghdlsynth-beta
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\verb{url}
\verb https://github.com/tgingold/ghdlsynth-beta
\endverb
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\verb https://github.com/daveshah1/nextpnr-xilinx
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\endverb
\verb{url}
\verb https://www.youtube.com/playlist?list=PLowKtXNTBypGqImE405J2565dvjafglHU
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\endentry
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\verb{url}
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\verb{url}
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22
main.bcf
View file

@ -2127,6 +2127,7 @@
<!-- SECTION 0 -->
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@ -2171,7 +2172,7 @@
<bcf:citekey order="40">ghdl</bcf:citekey>
<bcf:citekey order="41">gtkwave</bcf:citekey>
<bcf:citekey order="42">yosys</bcf:citekey>
<bcf:citekey order="43">yosys</bcf:citekey>
<bcf:citekey order="43">ghdlsynth-beta</bcf:citekey>
<bcf:citekey order="44">nextpnr-xilinx</bcf:citekey>
<bcf:citekey order="45">prjxray</bcf:citekey>
<bcf:citekey order="46">open-fpga-loader</bcf:citekey>
@ -2185,3 +2186,22 @@
<bcf:citekey order="53">nextpnr-xilinx</bcf:citekey>
<bcf:citekey order="54">prjxray</bcf:citekey>
<bcf:citekey order="55">liteeth</bcf:citekey>
<bcf:citekey order="56">riscv-compliance</bcf:citekey>
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[0] Config.pm:304> INFO - This is Biber 2.13
[0] Config.pm:307> INFO - Logfile is 'main.blg'
[21] biber:315> INFO - === Thu Mar 26, 2020, 17:07:44
[34] Biber.pm:375> INFO - Reading 'main.bcf'
[95] Biber.pm:905> INFO - Found 17 citekeys in bib section 0
[107] Biber.pm:4196> INFO - Processing section 0
[107] Utils.pm:75> INFO - Globbing data source './bibliographies/DP.bib'
[107] Utils.pm:91> INFO - Globbed data source './bibliographies/DP.bib' to ./bibliographies/DP.bib
[117] Biber.pm:4373> INFO - Looking for bibtex format file './bibliographies/DP.bib' for section 0
[119] bibtex.pm:1462> INFO - LaTeX decoding ...
[134] bibtex.pm:1281> INFO - Found BibTeX data source './bibliographies/DP.bib'
[170] UCollate.pm:68> INFO - Overriding locale 'de-DE' defaults 'variable = shifted' with 'variable = non-ignorable'
[170] UCollate.pm:68> INFO - Overriding locale 'de-DE' defaults 'normalization = NFD' with 'normalization = prenormalized'
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[187] bbl.pm:751> INFO - Output to main.bbl
[28] biber:315> INFO - === Fri Mar 27, 2020, 13:01:57
[44] Biber.pm:375> INFO - Reading 'main.bcf'
[102] Biber.pm:905> INFO - Found 30 citekeys in bib section 0
[113] Biber.pm:4196> INFO - Processing section 0
[113] Utils.pm:75> INFO - Globbing data source './bibliographies/DP.bib'
[114] Utils.pm:91> INFO - Globbed data source './bibliographies/DP.bib' to ./bibliographies/DP.bib
[114] Utils.pm:75> INFO - Globbing data source './bibliographies/AB.bib'
[114] Utils.pm:91> INFO - Globbed data source './bibliographies/AB.bib' to ./bibliographies/AB.bib
[124] Biber.pm:4373> INFO - Looking for bibtex format file './bibliographies/DP.bib' for section 0
[125] bibtex.pm:1462> INFO - LaTeX decoding ...
[140] bibtex.pm:1281> INFO - Found BibTeX data source './bibliographies/DP.bib'
[159] Biber.pm:4373> INFO - Looking for bibtex format file './bibliographies/AB.bib' for section 0
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@ -6,33 +6,40 @@
\babel@toc {ngerman}{}
\babel@toc {english}{}
\contentsline {figure}{\numberline {i}{\ignorespaces Atari PBI Pinout;Source: \url {https://www.atarimagazines.com}\relax }}{2}{figure.caption.1}%
\contentsline {figure}{\numberline {ii}{\ignorespaces Digilent Analog Discovery 2;Source: \url {https://www.sparkfun.com/}\relax }}{4}{figure.caption.2}%
\contentsline {figure}{\numberline {iii}{\ignorespaces Layout of the DIN41612 Connectors on the Backplane\relax }}{5}{figure.caption.3}%
\contentsline {figure}{\numberline {iv}{\ignorespaces Measurement at around 1MHz bus clock on MS1\relax }}{6}{figure.caption.4}%
\contentsline {figure}{\numberline {v}{\ignorespaces The case with installed backplane\relax }}{7}{figure.caption.5}%
\contentsline {figure}{\numberline {vi}{\ignorespaces PC-16550D Pinout\cite {pc16550}\relax }}{8}{figure.caption.6}%
\contentsline {figure}{\numberline {vii}{\ignorespaces The schematic of the UART Module\relax }}{10}{figure.caption.7}%
\contentsline {figure}{\numberline {viii}{\ignorespaces Measurement of the 1.8432 MHz Output on J1\relax }}{11}{figure.caption.8}%
\contentsline {figure}{\numberline {ix}{\ignorespaces Measurement of a character transmission before and after MAX-232\relax }}{12}{figure.caption.9}%
\contentsline {figure}{\numberline {x}{\ignorespaces Pinout of the RJ-45 Plug; Src: \url {https://www.wti.com/}\relax }}{12}{figure.caption.10}%
\contentsline {figure}{\numberline {xi}{\ignorespaces Measurement of a character echo\relax }}{13}{figure.caption.11}%
\contentsline {figure}{\numberline {xii}{\ignorespaces Transmission of character A via the 16550 UART\relax }}{16}{figure.caption.12}%
\contentsline {figure}{\numberline {xiii}{\ignorespaces TLC-7528 Pinout\cite {tlc7528}\relax }}{18}{figure.caption.13}%
\contentsline {figure}{\numberline {xiv}{\ignorespaces IDT-7201 Pinout\cite {idt7201}\relax }}{19}{figure.caption.14}%
\contentsline {figure}{\numberline {xv}{\ignorespaces TLC-7528 in voltage modet\cite {tlc7528}\relax }}{20}{figure.caption.15}%
\contentsline {figure}{\numberline {xvi}{\ignorespaces Measurement of a generated SAW signal via the TLC7528\relax }}{20}{figure.caption.16}%
\contentsline {figure}{\numberline {xvii}{\ignorespaces The schematic of the DAC Module\relax }}{21}{figure.caption.17}%
\contentsline {figure}{\numberline {xviii}{\ignorespaces Measurement of a generated SAW signal with the FIFO Empty flag\relax }}{23}{figure.caption.18}%
\contentsline {figure}{\numberline {xix}{\ignorespaces A transmission between the FIFO and the DAC\relax }}{24}{figure.caption.19}%
\contentsline {figure}{\numberline {xx}{\ignorespaces A fifo store operation in contrast to the load operation\relax }}{24}{figure.caption.20}%
\contentsline {figure}{\numberline {xxi}{\ignorespaces Storage and retrieval of a sine to and from the FIFO\relax }}{26}{figure.caption.21}%
\contentsline {figure}{\numberline {xxii}{\ignorespaces Measuremet of the generated sine from the sine LUT on DACA and DACB\relax }}{26}{figure.caption.22}%
\contentsline {figure}{\numberline {xxiii}{\ignorespaces 3.3V to 5V conversion using the level shifter\relax }}{27}{figure.caption.23}%
\contentsline {figure}{\numberline {xxiv}{\ignorespaces 5V to 3.3V conversion using the level shifter\relax }}{28}{figure.caption.24}%
\contentsline {figure}{\numberline {xxv}{\ignorespaces The internal schematics of the level shifter\cite {lvlshift}\relax }}{29}{figure.caption.25}%
\contentsline {figure}{\numberline {xxvi}{\ignorespaces The internal clamping diodes of the Analog Discovery 2\cite {ad2}\relax }}{30}{figure.caption.26}%
\contentsline {figure}{\numberline {xxvii}{\ignorespaces The output of an example track part 1\relax }}{40}{figure.caption.27}%
\contentsline {figure}{\numberline {xxviii}{\ignorespaces The output of an example track part 2\relax }}{41}{figure.caption.28}%
\contentsline {figure}{\numberline {xxix}{\ignorespaces A regular beginning of the game\relax }}{46}{figure.caption.29}%
\contentsline {figure}{\numberline {ii}{\ignorespaces Digilent Analog Discovery 2;Source: \url {https://www.sparkfun.com/}\relax }}{5}{figure.caption.2}%
\contentsline {figure}{\numberline {iii}{\ignorespaces Layout of the DIN41612 Connectors on the Backplane\relax }}{6}{figure.caption.3}%
\contentsline {figure}{\numberline {iv}{\ignorespaces Measurement at around 1MHz bus clock on MS1\relax }}{7}{figure.caption.4}%
\contentsline {figure}{\numberline {v}{\ignorespaces The case with installed backplane\relax }}{8}{figure.caption.5}%
\contentsline {figure}{\numberline {vi}{\ignorespaces PC-16550D Pinout\cite {pc16550}\relax }}{9}{figure.caption.6}%
\contentsline {figure}{\numberline {vii}{\ignorespaces The schematic of the UART Module\relax }}{11}{figure.caption.7}%
\contentsline {figure}{\numberline {viii}{\ignorespaces Measurement of the 1.8432 MHz Output on J1\relax }}{12}{figure.caption.8}%
\contentsline {figure}{\numberline {ix}{\ignorespaces Measurement of a character transmission before and after MAX-232\relax }}{13}{figure.caption.9}%
\contentsline {figure}{\numberline {x}{\ignorespaces Pinout of the RJ-45 Plug; Src: \url {https://www.wti.com/}\relax }}{13}{figure.caption.10}%
\contentsline {figure}{\numberline {xi}{\ignorespaces Measurement of a character echo\relax }}{14}{figure.caption.11}%
\contentsline {figure}{\numberline {xii}{\ignorespaces Transmission of character A via the 16550 UART\relax }}{17}{figure.caption.12}%
\contentsline {figure}{\numberline {xiii}{\ignorespaces TLC-7528 Pinout\cite {tlc7528}\relax }}{19}{figure.caption.13}%
\contentsline {figure}{\numberline {xiv}{\ignorespaces IDT-7201 Pinout\cite {idt7201}\relax }}{20}{figure.caption.14}%
\contentsline {figure}{\numberline {xv}{\ignorespaces TLC-7528 in voltage modet\cite {tlc7528}\relax }}{21}{figure.caption.15}%
\contentsline {figure}{\numberline {xvi}{\ignorespaces Measurement of a generated SAW signal via the TLC7528\relax }}{21}{figure.caption.16}%
\contentsline {figure}{\numberline {xvii}{\ignorespaces The schematic of the DAC Module\relax }}{22}{figure.caption.17}%
\contentsline {figure}{\numberline {xviii}{\ignorespaces Measurement of a generated SAW signal with the FIFO Empty flag\relax }}{24}{figure.caption.18}%
\contentsline {figure}{\numberline {xix}{\ignorespaces A transmission between the FIFO and the DAC\relax }}{25}{figure.caption.19}%
\contentsline {figure}{\numberline {xx}{\ignorespaces A fifo store operation in contrast to the load operation\relax }}{25}{figure.caption.20}%
\contentsline {figure}{\numberline {xxi}{\ignorespaces Storage and retrieval of a sine to and from the FIFO\relax }}{27}{figure.caption.21}%
\contentsline {figure}{\numberline {xxii}{\ignorespaces Measuremet of the generated sine from the sine LUT on DACA and DACB\relax }}{27}{figure.caption.22}%
\contentsline {figure}{\numberline {xxiii}{\ignorespaces 3.3V to 5V conversion using the level shifter\relax }}{29}{figure.caption.23}%
\contentsline {figure}{\numberline {xxiv}{\ignorespaces 5V to 3.3V conversion using the level shifter\relax }}{30}{figure.caption.24}%
\contentsline {figure}{\numberline {xxv}{\ignorespaces The internal schematics of the level shifter\cite {lvlshift}\relax }}{30}{figure.caption.25}%
\contentsline {figure}{\numberline {xxvi}{\ignorespaces The internal clamping diodes of the Analog Discovery 2\cite {ad2}\relax }}{31}{figure.caption.26}%
\contentsline {figure}{\numberline {xxvii}{\ignorespaces The output of an example track part 1\relax }}{42}{figure.caption.27}%
\contentsline {figure}{\numberline {xxviii}{\ignorespaces The output of an example track part 2\relax }}{43}{figure.caption.28}%
\contentsline {figure}{\numberline {xxix}{\ignorespaces A regular beginning of the game\relax }}{48}{figure.caption.29}%
\contentsline {figure}{\numberline {xxx}{\ignorespaces Screenshot of the resulting waveform in GTKWave\relax }}{53}{figure.caption.30}%
\contentsline {figure}{\numberline {xxxi}{\ignorespaces Block diagram of the video core\relax }}{58}{figure.caption.31}%
\contentsline {figure}{\numberline {xxxii}{\ignorespaces Diagram of VGA timing intervals\relax }}{59}{figure.caption.32}%
\contentsline {figure}{\numberline {xxxiii}{\ignorespaces Block diagram of the text renderer\relax }}{60}{figure.caption.33}%
\contentsline {figure}{\numberline {xxxiv}{\ignorespaces Block diagram of the WS2812 driver\relax }}{60}{figure.caption.34}%
\contentsline {figure}{\numberline {xxxv}{\ignorespaces Timing diagram for the WS2812 serial protocol\relax }}{61}{figure.caption.35}%
\contentsline {figure}{\numberline {xxxvi}{\ignorespaces Block diagram of the CPU core\relax }}{63}{figure.caption.36}%
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@ -4,22 +4,22 @@
\babel@toc {ngerman}{}
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\contentsline {lstlisting}{\numberline {I}Read and write routines for the 16550 UART}{13}{lstlisting.1}%
\contentsline {lstlisting}{\numberline {II}16550 INIT routines and single char transmission}{15}{lstlisting.2}%
\contentsline {lstlisting}{\numberline {III}16550 character echo}{16}{lstlisting.3}%
\contentsline {lstlisting}{\numberline {IV}SAW Generation for the DAC with FIFO}{24}{lstlisting.4}%
\contentsline {lstlisting}{\numberline {V}Sine LUT Generation}{25}{lstlisting.5}%
\contentsline {lstlisting}{\numberline {VI}DAC Sine Generation}{25}{lstlisting.6}%
\contentsline {lstlisting}{\numberline {VII}The avr.h header file}{30}{lstlisting.7}%
\contentsline {lstlisting}{\numberline {VIII}The routine function looped by the main}{32}{lstlisting.8}%
\contentsline {lstlisting}{\numberline {IX}The routine function for the UART}{32}{lstlisting.9}%
\contentsline {lstlisting}{\numberline {X}The routine function for the DAC}{33}{lstlisting.10}%
\contentsline {lstlisting}{\numberline {XI}The DAC operation modes}{34}{lstlisting.11}%
\contentsline {lstlisting}{\numberline {XII}The DAC waveform generation code}{34}{lstlisting.12}%
\contentsline {lstlisting}{\numberline {XIII}The ISR which fires every millisecond}{37}{lstlisting.13}%
\contentsline {lstlisting}{\numberline {XIV}The sound update function}{38}{lstlisting.14}%
\contentsline {lstlisting}{\numberline {XV}The character ingest function}{42}{lstlisting.15}%
\contentsline {lstlisting}{\numberline {XVI}The command parsing function}{43}{lstlisting.16}%
\contentsline {lstlisting}{\numberline {XVII}The command execution routine}{44}{lstlisting.17}%
\contentsline {lstlisting}{\numberline {I}Read and write routines for the 16550 UART}{14}{lstlisting.1}%
\contentsline {lstlisting}{\numberline {II}16550 INIT routines and single char transmission}{16}{lstlisting.2}%
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\contentsline {lstlisting}{\numberline {IV}SAW Generation for the DAC with FIFO}{25}{lstlisting.4}%
\contentsline {lstlisting}{\numberline {V}Sine LUT Generation}{26}{lstlisting.5}%
\contentsline {lstlisting}{\numberline {VI}DAC Sine Generation}{26}{lstlisting.6}%
\contentsline {lstlisting}{\numberline {VII}The avr.h header file}{33}{lstlisting.7}%
\contentsline {lstlisting}{\numberline {VIII}The routine function looped by the main}{34}{lstlisting.8}%
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\contentsline {lstlisting}{\numberline {XIII}The ISR which fires every millisecond}{40}{lstlisting.13}%
\contentsline {lstlisting}{\numberline {XIV}The sound update function}{40}{lstlisting.14}%
\contentsline {lstlisting}{\numberline {XV}The character ingest function}{44}{lstlisting.15}%
\contentsline {lstlisting}{\numberline {XVI}The command parsing function}{45}{lstlisting.16}%
\contentsline {lstlisting}{\numberline {XVII}The command execution routine}{46}{lstlisting.17}%
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\babel@toc {english}{}

18
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4
main.tex
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@ -90,10 +90,6 @@ des generischen Maskulinums angewendet. Es wird an dieser Stelle darauf
hingewiesen, dass die ausschlie"sliche Verwendung der m"annlichen Form
geschlechtsunabh"angig verstanden werden soll.
This thesis is written in the language form if the generic masculin for improved
readability. It is pointed out that all masculin-only uses may and should be
interpreted as gender neutral.
%====================================================================================
\clearpage\vfill\newpage{}
%====================================================================================

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\babel@toc {ngerman}{}
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\contentsline {section}{Gendererklärung}{i}{Doc-Start}%
\contentsline {section}{Kurzfassung/Abstract}{ii}{Doc-Start}%
\babel@toc {ngerman}{}
\babel@toc {ngerman}{}
\contentsline {section}{Result}{iii}{Doc-Start}%
\babel@toc {english}{}
\contentsline {section}{\numberline {1}Task description}{1}{section.1}%
\contentsline {subsection}{\numberline {1.1}Hardware}{1}{subsection.1.1}%
\contentsline {section}{\numberline {2}Hardware peripherials}{2}{section.2}%
\contentsline {subsection}{\numberline {2.1}Parallel bus}{2}{subsection.2.1}%
\contentsline {subsubsection}{\numberline {2.1.1}Address Bus}{3}{subsubsection.2.1.1}%
\contentsline {subsection}{\numberline {2.2}Data Bus}{3}{subsection.2.2}%
\contentsline {subsection}{\numberline {2.3}Control Bus}{3}{subsection.2.3}%
\contentsline {subsubsection}{\numberline {2.3.1}Master Reset}{3}{subsubsection.2.3.1}%
\contentsline {subsubsection}{\numberline {2.3.2}Write Not}{4}{subsubsection.2.3.2}%
\contentsline {subsubsection}{\numberline {2.3.3}Read Not}{4}{subsubsection.2.3.3}%
\contentsline {subsubsection}{\numberline {2.3.4}Module Select 1 and 2 Not}{4}{subsubsection.2.3.4}%
\contentsline {subsection}{\numberline {2.4}Testing and Measurement}{4}{subsection.2.4}%
\contentsline {subsubsection}{\numberline {2.4.1}Measurements}{4}{subsubsection.2.4.1}%
\contentsline {subsubsection}{\numberline {2.4.2}Testing}{5}{subsubsection.2.4.2}%
\contentsline {subsection}{\numberline {2.5}Backplane}{5}{subsection.2.5}%
\contentsline {subsubsection}{\numberline {2.5.1}Termination resistors}{6}{subsubsection.2.5.1}%
\contentsline {subsection}{\numberline {2.6}Case}{7}{subsection.2.6}%
\contentsline {subsection}{\numberline {2.7}Serial Console}{9}{subsection.2.7}%
\contentsline {subsubsection}{\numberline {2.7.1}16550 UART}{9}{subsubsection.2.7.1}%
\contentsline {subsubsection}{\numberline {2.7.2}MAX-232}{10}{subsubsection.2.7.2}%
\contentsline {subsubsection}{\numberline {2.7.3}Schematics}{10}{subsubsection.2.7.3}%
\contentsline {paragraph}{Element Description}{12}{figure.caption.7}%
\contentsline {subsubsection}{\numberline {2.7.4}Demonstration Software}{14}{subsubsection.2.7.4}%
\contentsline {paragraph}{Transmit code}{14}{figure.caption.11}%
\contentsline {paragraph}{Echo code}{17}{figure.caption.12}%
\contentsline {subsection}{\numberline {2.8}Audio Digital-Analog-Converter}{18}{subsection.2.8}%
\contentsline {subsubsection}{\numberline {2.8.1}TLC 7528 Dual R2R Ladder DAC}{19}{subsubsection.2.8.1}%
\contentsline {subsubsection}{\numberline {2.8.2}IDT7201 CMOS FIFO Buffer}{19}{subsubsection.2.8.2}%
\contentsline {subsubsection}{\numberline {2.8.3}Theory verfication}{20}{subsubsection.2.8.3}%
\contentsline {subsubsection}{\numberline {2.8.4}Schematics}{21}{subsubsection.2.8.4}%
\contentsline {paragraph}{Element Description}{23}{figure.caption.17}%
\contentsline {paragraph}{NE55 Clock Source}{24}{figure.caption.17}%
\contentsline {subsubsection}{\numberline {2.8.5}Demonstration Software}{24}{subsubsection.2.8.5}%
\contentsline {paragraph}{SAW Generator}{24}{subsubsection.2.8.5}%
\contentsline {paragraph}{Sine Generator}{26}{lstnumber.4.11}%
\contentsline {section}{\numberline {3}Addressing DACA and DACB}{28}{section.3}%
\contentsline {subsection}{\numberline {3.1}FPGA to Hardware interface}{28}{subsection.3.1}%
\contentsline {subsubsection}{\numberline {3.1.1}Measurement error}{31}{subsubsection.3.1.1}%
\contentsline {section}{\numberline {4}Textadventure}{31}{section.4}%
\contentsline {subsection}{\numberline {4.1}General Implementation details}{32}{subsection.4.1}%
\contentsline {subsubsection}{\numberline {4.1.1}General definitions and pinout of the AVR}{32}{subsubsection.4.1.1}%
\contentsline {subsubsection}{\numberline {4.1.2}Read and Write routines}{34}{subsubsection.4.1.2}%
\contentsline {subsubsection}{\numberline {4.1.3}UART and DAC update polling}{34}{subsubsection.4.1.3}%
\contentsline {subsection}{\numberline {4.2}DAC sound generation}{35}{subsection.4.2}%
\contentsline {subsubsection}{\numberline {4.2.1}DAC modes}{35}{subsubsection.4.2.1}%
\contentsline {subsubsection}{\numberline {4.2.2}Tones and Tracks}{40}{subsubsection.4.2.2}%
\contentsline {subsubsection}{\numberline {4.2.3}Track switching}{44}{subsubsection.4.2.3}%
\contentsline {subsection}{\numberline {4.3}User command interpretation}{44}{subsection.4.3}%
\contentsline {subsubsection}{\numberline {4.3.1}Command structure and parsing}{44}{subsubsection.4.3.1}%
\contentsline {subsubsection}{\numberline {4.3.2}Command parameters}{46}{subsubsection.4.3.2}%
\contentsline {subsection}{\numberline {4.4}Gameplay}{47}{subsection.4.4}%
\contentsline {subsection}{\numberline {4.5}Memory constraints}{49}{subsection.4.5}%
\contentsline {part}{I\hspace {1em}A short introduction to VHDL}{50}{part.1}%
\contentsline {section}{\numberline {5}Prerequisites}{50}{section.5}%
\contentsline {section}{\numberline {6}Creating a design}{50}{section.6}%
\contentsline {section}{\numberline {7}Simulating a design}{52}{section.7}%
\contentsline {section}{\numberline {8}Synthesizing a design}{53}{section.8}%
\contentsline {part}{II\hspace {1em}Meta}{54}{part.2}%
\contentsline {section}{\numberline {9}History}{54}{section.9}%
\contentsline {section}{\numberline {10}Tooling}{56}{section.10}%
\contentsline {subsection}{\numberline {10.1}Vendor Tools}{56}{subsection.10.1}%
\contentsline {subsection}{\numberline {10.2}Free Software Tools}{56}{subsection.10.2}%
\contentsline {section}{\numberline {11}Peripherals}{57}{section.11}%
\contentsline {subsection}{\numberline {11.1}UART}{57}{subsection.11.1}%
\contentsline {subsection}{\numberline {11.2}DVI graphics}{57}{subsection.11.2}%
\contentsline {subsubsection}{\numberline {11.2.1}VGA timing}{57}{subsubsection.11.2.1}%
\contentsline {subsubsection}{\numberline {11.2.2}Text renderer}{58}{subsubsection.11.2.2}%
\contentsline {subsubsection}{\numberline {11.2.3}TMDS encoder}{59}{subsubsection.11.2.3}%
\contentsline {subsection}{\numberline {11.3}Ethernet}{59}{subsection.11.3}%
\contentsline {subsection}{\numberline {11.4}WS2812 driver}{60}{subsection.11.4}%
\contentsline {subsection}{\numberline {11.5}DRAM}{61}{subsection.11.5}%
\contentsline {subsection}{\numberline {11.6}External Bus}{61}{subsection.11.6}%
\contentsline {section}{\numberline {12}Testing}{62}{section.12}%
\contentsline {subsection}{\numberline {12.1}RISC-V Compliance Tests}{62}{subsection.12.1}%
\contentsline {part}{III\hspace {1em}The Core}{62}{part.3}%
\contentsline {section}{\numberline {13}Overview}{63}{section.13}%
\contentsline {section}{\numberline {14}Control}{63}{section.14}%
\contentsline {section}{\numberline {15}Decoder}{64}{section.15}%
\contentsline {section}{\numberline {16}Registers}{65}{section.16}%
\contentsline {section}{\numberline {17}Arithmetic and Logic Unit (ALU)}{66}{section.17}%
\contentsline {section}{\numberline {18}Control and Status Registers (CSR)}{66}{section.18}%
\contentsline {section}{\numberline {19}Memory Arbiter}{67}{section.19}%
\contentsline {section}{\numberline {20}Exception Control}{68}{section.20}%
\babel@toc {ngerman}{}
\contentsline {section}{\numberline {21}Erkl"arung der Eigenst"andigkeit der Arbeit}{70}{section.21}%
\babel@toc {english}{}
\contentsline {section}{\numberline {I\tmspace +\thickmuskip {.2777em}}List of Figures}{I}{section.1}%
\contentsline {section}{\numberline {II\tmspace +\thickmuskip {.2777em}}List of Tables}{II}{section.2}%
\contentsline {section}{\numberline {III\tmspace +\thickmuskip {.2777em}}Listings}{II}{section.3}%
\contentsline {section}{Anhang}{V}{section.3}%

6
planung/DP/aufgabenstellung.tex
View file

@ -3,7 +3,7 @@
Due to the recurring questions in the environment of the Hackerspace Innsbruck
about the internal workings of a computer system and the lack of material to
demonstrate these, hardware should be developed for educational purposes.
This hardware should not be to complex to understand but still demonstrate basic
This hardware should not be too complex to understand but still demonstrate basic
tasks of a computer system. The targeted computing tasks are human interface
device controllers, under which a \textbf{D}igital to \textbf{A}nalog
\textbf{C}onverter\footnote{From now on reffered to simply as DAC} and a serial
@ -11,10 +11,10 @@ console with TIA-/EIA-232 compliant voltage levels were chosen. For these
peripherials schematics and a working implementation in the hardware building
style of the hackerspace should be built. All nescessary hardware will be
provided by the Hackerspace. If possible already present hardware should be
used, if impossible new one will be ordered. All schematics should, whenether
used, if impossible new one will be ordered. All schematics should, where
possible be written in open-source software such as Kicad or GNU-EDA.
If possible software-examples should be written as well, though the complexity
of these was coupled to the time left to spend on the project. Software should
of these are coupled to the time left to spend on the project. Software should
be written in C, the coding convention is left to the implementer.

2
preamble.tex
View file

@ -149,7 +149,7 @@
\makeindex
%%% BibLaTeX settings
\usepackage[style = verbose, dashed=false, citestyle = ieee]{biblatex}
\usepackage[citestyle = ieee]{biblatex}
\usepackage{csquotes}
\addbibresource{./bibliographies/DP.bib}
\addbibresource{./bibliographies/AB.bib}

12
sections/DP/CASE_BACKPLANE/main.tex
View file

@ -4,7 +4,7 @@ To connect the modules to the microprocessor, many pins need to be connected
straight through. For this purpose a backplane was chosen where DIN41612
connectors can be used. These connectors were chosen for their large pin count
(96 pins) and their availability. The backplane connects all 96-pins straight
through. With the 6 outer left and right pins connected for VCC and ground,
through. With the 6 outer left and right pins connected for VCC and ground
as can be seen in figure \ref{fig:schem_back_conn}.
\begin{figure}[H]
@ -15,7 +15,7 @@ as can be seen in figure \ref{fig:schem_back_conn}.
\subsubsection{Termination resistors}
In constrast to other systems using this backplane, no termination resistors
In constrast to other systems using this backplane no termination resistors
were used. This makes the bus more prone to refelctions, however these were not
a problem during development with the maximum transmission rate of 1MHz, as can
be seen in the sample recording in figure \ref{fig:reflex}
@ -39,16 +39,16 @@ be seen in the sample recording in figure \ref{fig:reflex}
\label{fig:reflex}
\end{figure}
The ripple seen in figure \ref{fig:reflex} are most likely due to
The ripple seen in figure \ref{fig:reflex} is most likely due to
the sample rate of the Oszilloscope, which is around 10Mhz after an average
filter has been applied. The measurement was performed on the finished project,
filter has been applied. The measurement was performed on the finished project
with all cards installed.
\subsection{Case}
The case for the backplane was provided by the hackerspace, and is meant for
The case for the backplane was provided by the hackerspace and is meant for
installation in a rack. The case is meant for installation of cards in the
EUROCARD format, therfore all modules were built by this formfactor.
EUROCARD format, therefore all modules were built by this formfactor.
\begin{figure}[H]
\includegraphics[width=\textwidth, angle=0]{pics/case}

15
sections/DP/MEAS_TEST/main.tex
View file

@ -1,17 +1,17 @@
\subsection{Testing and Measurement}
For functional testing and verification of implementation goals, measurements
needed to be performed invarious different ways and testing software was
For functional testing and verification of implementation goals measurements
needed to be performed in various different ways and testing software was
required.
\subsubsection{Measurements}
Measurements were performed, if not noted otherwise, with the Analog Discovery
2 from Digilent as it has 16bit digital I/O Pins as well a a Waveform generator
and 2 differential oszilloscope inputs\cite{ad2}. These were for all nescessary
measurements enough. Though due to the size and construction of the device,
which can be seen in figure \ref{fig:ad2}
errors wer encountered while performing the measurements. These are noted on
and 2 differential oszilloscope inputs\cite{ad2}. These were enough for all
nescessary measurements. Though due to the size and construction of the device,
which can be seen in figure \ref{fig:ad2},
errors were encountered while performing the measurements. These are noted on
occurance.
\begin{figure}[H]
@ -24,9 +24,8 @@ occurance.
\subsubsection{Testing}
All testing was performed with an Atmel ATMega2560 due to it's large amount
of I/O pins, 5V I/O which is the more common voltage level on CMOS
of I/O pins, 5V I/O, which is the more common voltage level on CMOS
peripherials, way of addressing pins (8 at a time) and availability.
\cite{atmega2560} All
testing software was written for this ATMega and compiled using the avr-gcc
from the GNU-Project.

6
sections/DP/PARALLELBUS/main.tex
View file

@ -23,7 +23,7 @@ layout of the Atari Parallel Bus Interface is shown as used on the Atari 800XL.
\subsubsection{Address Bus}
The address bus contains the nescessary data lines for addressing the individual
registers of the Serial connection and the uart. On any modern system this bus
registers of the Serial connection and the UART. On any modern system this bus
is from 16 to 64 bits wide. For our implementation the bus size was chosen to
be 8 bit, which is multiple times the amount of needed address space, but
is the smallest addressable unit on most microcontroller architectures and
@ -40,7 +40,7 @@ bus is bidirectional.
Control bus is a term which referes to any control lines (such as read and write
lines or clock lines) which are neither address nor data bus. The control bus
in our case needed to be 5 bits wide and consists of:
in our case is 5 bits wide and consists of:
\begin{itemize}
\item{$MR$ ... Master Reset}
@ -54,7 +54,7 @@ in our case needed to be 5 bits wide and consists of:
A high level on the $MR$ lane signals to the peripherials that a reset of all
registers and states should occure. This is needed for the serial console and
the dac.
the DAC.
\subsubsection{Write Not}
A low level on the $\lnot WR$ lane signals the corresponding modules that the

52
sections/DP/UART/main.tex
View file

@ -2,25 +2,25 @@
One core part of any computer systems is it's way to get human input. On older
systems, and even today on server machines, this is done via a serial console.
On this serial console, characters are transmitted in serial, which means bit
On this serial console characters are transmitted in serial, which means bit
by bit over the same line. The voltage levels used in these systems vary from
5V to 3.3V or +-10V. The most common standart for these voltage levels is the
5V to 3.3V or +-10V. The most common standard for these voltage levels is the
former RS-232\footnote{RS... Recommended Standard} or as it should be called
now TIA-\footnote{TIA...Telecommunications Industry
Association}/EIA-\footnote{EIA.. Electronic Industries Alliance}232. Voltage-
levels as per TIA-/EIA Standard are not practical to handle over short
distances to handle however, so other voltages are used on most interface chips
now, TIA-\footnote{TIA...Telecommunications Industry
Association}/EIA-\footnote{EIA.. Electronic Industries Alliance}232.\cite{rs232}
Voltage-levels ,as per TIA-/EIA- standard, are not practical to handle over short
distances however, so other voltages are used on most interface chips
and need to be converted.
\subsubsection{16550 UART}
The 16550 UART\footnote{Uinversal Asynchronous Receiver and Transmitter} is a
very common interface chip for serial communications. It produces 5V logic
levels as output on TX and needs the same as input on RX. Thoug common for a
levels as output on TX and needs the same as input on RX. Though common for a
UART, these voltage levels need to be converted to TIA-/EIA-232 levels for a
more common interface.
The 16550 UART is, in it's core a 16450 UART, but has been given a FIFO
The 16550 UART is in it's core a 16450 UART, but has been given a FIFO
\footnote{First-In First-Out} buffer. It needs three address lines, and 8
data lines, which can be seen in figure \ref{fig:16550_pinout}
@ -32,17 +32,17 @@ data lines, which can be seen in figure \ref{fig:16550_pinout}
\end{figure}
In figure \ref{fig:16550_pinout} the most important lanes are the SIN and
sout lanes, as they contain the serial data to and from the 16550 UART.
SOUT lanes, as they contain the serial data to and from the 16550 UART.
\subsubsection{MAX-232}
To convert the voltage levels of the 16550 UART to levels compliant wit
TIA-/EIA-232 levels, the MAX-232 is used. It has two transmitters and two
receivers side and generates the needed voltage levels via an internal voltage
To convert the voltage levels of the 16550 UART to levels compliant with
TIA-/EIA-232 levels the MAX-232 is used. It has two transmitters and two
receivers and generates the needed voltage levels via an internal voltage
pump\cite{max232}.
\subsubsection{Schematics}
Based on the descriptions in the datasheets the schematic in figure
Based on the descriptions in the datasheets, the schematic in figure
\ref{fig:schem_uart} was developed.
\begin{figure}[H]
@ -56,24 +56,24 @@ Based on the descriptions in the datasheets the schematic in figure
The quartz oszillator Y1 is the clock source for the Baud Rate generation and
was chosen with 1.8432 MHz for availability reasons and because it is the lowest
ozillator from which all common baud rates can still be derived from
ozillator from which all common baud rates can still be derived
\cite{pc16550}.
Resistors R1 and R2 are for stability and functionality of the Oszillator
nescessary as per datasheet. The resulting frequency can bemeasured via
J1, the measurement can be seen in \ref{fig:uartquartz}. C1 is used to
nescessary as per datasheet. The resulting frequency can be measured via
J1 as can be seen in figure \ref{fig:uartquartz}. C1 is used to
stabilize the
voltage for the 16550 UART and is common practice. Via JP1 the UART can be
transformed into a USRT where the receiver is synchronized to the transmitter
transformed into a USRT, where the receiver is synchronized to the transmitter
via a clock line. This mode has, however, not been tested, and the clock needs
to be 16 times the receiver clock rate\cite{pc16550}. The final output of the
16550 UART can be used and measured via J2, as shown in figure \ref{fig:uart232}
. Before the UART on J2 can be use however, the Jumpers JP2 and JP3 need to be
removed as otherwise the MAX-232 will short out with the incoming signal.
capacitors C4, C6, C7, C7 and C8 are for the voltage pump as defined in the
. Before the UART on J2 can be used however, the Jumpers JP2 and JP3 need to be
removed, as otherwise the MAX-232 will short out with the incoming signal.
Capacitors C4, C6, C7 and C8 are for the voltage pump as defined in the
datasheet\cite{max232}. R4 and R5 have been suggested by the supervisor in
order toavoid damage to the MAX-232. The RJ-45 plug is used to transmit the
order to avoid damage to the MAX-232. The RJ-45 plug is used to transmit the
TIA-/EIA-232 signal, rather than the more common D-SUB connector, because the
RJ-45 connector fits on a 2.54mm grid. The Pinout onthe RJ-45 plug can be seen
RJ-45 connector fits on a 2.54mm grid. The Pinout of the RJ-45 plug can be seen
in figure \ref{fig:rs232rj45}. C5 has the same functionality for the
MAX-232 as the C1 has to the 16550-UART.
@ -122,7 +122,7 @@ MAX-232 as the C1 has to the 16550-UART.
\subsubsection{Demonstration Software}
To demonstrate the functionality and prove, that the schematic has no underlying
To demonstrate the functionality and prove that the schematic has no underlying
error, a program which regularly transmits a character was written as well as
a simple echo program, which transmits all received characters. Both programs
transmit 8 bit characters without parity at 38400 Baud. The output for program
@ -149,8 +149,8 @@ figure \ref{fig:232_echo}.
\end{figure}
\paragraph{Transmit code}
The transmit code regularly transmits the letter capital A via the 16550 UART,
but before it can do this it needs to perform some initialisations. The
The transmit code regularly transmits the letter capital A via the 16550 UART.
Before it can do this it needs to perform some initialisations. The
functions shown in listing \ref{lst:16550-general} are the read and write
routines for accessing the 16550 UART. These routines also apply to the echo
code.
@ -187,7 +187,7 @@ SOUT lane of the 16550 UART can be seen in figure \ref{fig:16550A}
\paragraph{Echo code}
The echo code permanently polls the 16550 UART wether a character has been
received, and if yes, reads it from the receiver holding register andwrites it
received, and if yes, reads it from the receiver holding register and writes it
back to the tx holding register. The output of this code can be seen in figure
\ref{fig:232_echo}. The initialisation is practically the same as for the
transmission code, as well as the read and write routines in listing

65
sections/DP/dac/main.tex
View file

@ -2,21 +2,21 @@
A digital to analog converter takes a digital number and converts it to a
analog signal. The output of one such conversion is called a sample. With
enough samples per second various different waveforms can be produced which,
enough samples per second various different waveforms can be produced, which,
when amplified and put onto a speaker, can be heared by the human ear as a tone.
With various tones in series a melody can be produced, which is what the DAC in
this implementation does.
\subsubsection{TLC 7528 Dual R2R Ladder DAC}
The TLC 7528 is a Dual output Parallel input R2R Ladder DAC with a maximum
sample rate of 10MHz\cite{tlc7528} and which (should be) is monotonic over the
The TLC 7528 is a Dual output parallel input R2R Ladder DAC with a maximum
sample rate of 10MHz \cite{tlc7528}, and which (should be) is monotonic over the
entire D/A Conversion Range. The TLC-7528 was the only component chosen, where
availability was not a factor, but rather due to it's design.It is the cheapest
dual R2R Ladder dac which takes \textbf{PARALLEL} input, which was an important
availability was not a factor, but rather it's design. It is the cheapest
dual R2R Ladder dac which takes \textbf{PARALLEL} input, which is an important
feature, because the backbone of the project is its parallel bus. Further the
DAC was developed for audio aplications\cite{tlc7528} obvious and
the TLC-7528 was the only IC available as DIP
DAC was developed for audio aplications\cite{tlc7528} which made its use obvious
and the TLC-7528 was the only IC available as DIP
\footnote{DIP... Dual Inline Package}, of which the pinout can be seen in figure
\ref{fig:tlc7528_pinout}
@ -47,13 +47,14 @@ parallel bus for interaction with the 16550 UART.
Before tests of the complete unit were conducted, the functionality of the
device and the validity of the knowledge of operations were performed. For that
the DAC was directl connected to the ATMega without the FIFO infront of it.
the DAC was directly connected to the ATMega without the FIFO in front of it.
A saw was generated on only the DACA channel, which was put into voltage mode
as described in the datasheet\cite{tlc7528} and seen in figure
\ref{fig:tlc7528_volt}. After the result seen in \ref{fig:tlc7528_saw_nonlin}
was found a lot of effort was put in to determine the source of the heavy noise,
however no obvious conclusion can be made, execpt that it comes from the DAC
itself and is consistant over whatever frequency used. A damaged IC could be
\ref{fig:tlc7528_volt}.
After the result seen in figure \ref{fig:tlc7528_saw_nonlin}
was measured, a lot of effort was put in to determine the source of the heavy
noise, however no obvious conclusions can be made, execpt that it comes from the
DAC itself and is consistant over whatever frequency used. A damaged IC could be
the reason or a sloppy production progress. Filters can be used to reduce the
noise, however this was not done in this thesis, as the generated audio does
not seem to suffer from these non-linearities as badly as when measured
@ -107,12 +108,12 @@ $\lnot MODRD = \lnot RD \lor \lnot MS2$
$\lnot MODWR = \lnot WR \lor \lnot MS2$
On a read access, the output enable of the D-Latch becomes low, which writes
On a read access the output enable of the D-Latch becomes low, which writes
the status bits of the FIFO onto the data bus. C1, C2 and C3 are for stability
reasons and are good practice, similar to the UART module. 74HC00 is a quad
reasons and are good practice similar to the UART module. 74HC00 is a quad
NAND-Gate\cite{74hc00} which is only used for inversion, chosen, like the
74HC374, for availability reasons. The A part of the NAND-Gate inverts the $MR$
signal from the bus to a $\not MR$ signal as the FIFOs reset is low active.
signal from the bus to a $\lnot MR$ signal, as the FIFOs reset is low active.
The B part of the NAND-Gate inverts the FIFO Empty flag. It's output is
connected to the $\lnot WR$ input of the DAC, which means that the DAC doesn't
convert the input anymore, if the FIFO Empty flag is set to low.
@ -123,14 +124,15 @@ samling rate of CD-Audio\cite{iec60908}. Resistors R9 and R10 togehter with C7
form the Oscillator part of the NE55. C4 is for stability reasons and doesn't
define the frequency of the oscillator.
The generated clock is used for the $\lnot R$ of the FIFO and inverted on the
The generated clock is used for the $\lnot RD$ of the FIFO and inverted on the
DAC, which makes the data available on the output before being stored into the
DAC as it receives the signal to store the data after the FIFO makes it
available on the bus.
The DAC is operated in voltage mode as described in \ref{fig:tlc7528_volt},
with it's voltage source beeing available at either 3.472Vpp for professional
audio or 0.894Vpp for consumer audio, as defined per convention.\cite{audiob}
with it's voltage source beeing available at either $3.472V_{pp}$ for
professional
audio or $0.894V_{pp}$ for consumer audio, as defined per convention.\cite{audiob}
The voltage source can be controlled via Jumper JP1.
C5 and C6 together with the load resistance on the audio jack form a high pass
@ -148,18 +150,22 @@ poweroff.
\paragraph{NE55 Clock Source}
Though used as a clovk source, the NE555 is a bad clock source if a stable
clock is needed, because it varies widely with temperature, preasure and aging
elements. A better solution would have been a quartz which is divided down to
the desired frequency, whichwas what CD Drives used to do, but more commonly in
modern CD Drives, an ASIC with internal PLL is used, thus the required quartz
can no longer be sourced.
Though used as a clock source, the NE555 is a bad clock source, if a stable
frequency is needed, because it varies widely with temperature, preasure and
ageing
elements. A better solution would have been a quartz, which is divided down to
the desired frequency, which was what CD-Drives used to do, but more commonly in
modern CD Drives, an ASIC
\footnote{ASIC...Application-specific integrated circuit}
with an internal PLL is used, thus the required quartz can no longer be sourced
via conventional electronic resellers.
\subsubsection{Demonstration Software}
\paragraph{SAW Generator}
To prove read and write access from the D Flip-Flop and the FIFO are working,
To prove that read and write access from the D Flip-Flop and the FIFO are
working,
the same saw signal has been generated as in figure \ref{fig:tlc7528_saw_nonlin}
, however the signal was put into the FIFO and not the DAC directly. The
resulting saw wave can be seen in figure \ref{fig:tlc7528_saw_fifo} together
@ -188,8 +194,8 @@ and starts/ends the complete D/A conversion, until further data is received.
\end{figure}
The time difference betwen a stor and complete write cycle can be seen in figure
\ref{fig:fifo_dac_store}, while the figure \ref{fig:fifo_dac} shows the
The time difference betwen a store and complete write cycle can be seen in figure
\ref{fig:fifo_dac_store}, while figure \ref{fig:fifo_dac} shows the
transmission between dac and fifo in more detail.
\begin{figure}[H]
\centering
@ -207,8 +213,7 @@ transmission between dac and fifo in more detail.
The initialisation routines and read/write operations for the DAC module are
basically the same as for the UART module, and have thus been ommitted. They
can be seen in listing \ref{lst:16550-transmit} and partially in listing
\ref{lst:16550-transmit}.
can be seen in listing \ref{lst:16550-transmit}.
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
@ -223,7 +228,7 @@ As a further example a sine was generated and played on the DAC. The ATMega
itself is not powerful enough to generate the sine on the fly, therefore a
lookup-table had to be generated, which can be seen in listing
\ref{lst:dac_sine_lut}. How the data is transmitted to the FIFO can be seen
in listing \ref{lst:dac_sine} and figure \ref{fig:fifo_sine_store} and the
in listing \ref{lst:dac_sine} and figure \ref{fig:fifo_sine_store}, and the
resulting sine on both output channels can be seen in figure
\ref{fig:sine_dacab}.

2
sections/DP/textadv/main.tex
View file

@ -25,7 +25,7 @@ RD_SHIFT, CS_UART_SHIFT and CS_DAC_SHIFT are used to indicate the position of
the corresponding control lines inside the control bus register. All other
shift values are the same bitordering in input as in output.
The BUS_HOLD_US is used to tell the avr how many microsecons it takes for the
The BUS_HOLD_US is used to tell the avr how many microseconds it takes for the
data bus to be latched into input register of the devices on write or how long
it takes for the data bus to become stable on read. A delay of less than 1
microsecond is not possible due to limitations of the AVR and the bus capacity,

12
sections/abstract.tex
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@ -3,21 +3,21 @@
Diese Diplomarbeit beschäftigt sich mit der Arbeitsweise von Prozessoren
und Prozessorperipherie in moderner und traditioneller Form. Sie versucht
anschaulich den
Aufbau eines Computersystems in Hard- und Software veranschaulichen
sowie diesen erklären. Dafür wurde auf einem XILINX FPGA ein RISC-V32I Prozessor
in VHDL
Aufbau eines Computersystems in Hard- und Software zu veranschaulichen
sowie diesen zu erklären. Dafür wurde auf einem XILINX FPGA ein RISC-V32I
Prozessor in VHDL
implementiert sowie diverse Parallelbus gebundene Hardwareperipherie entwickelt
und gebaut. Als Harwareperipherie wurde ein 8-Bit 2-Kanal DAC und eine serielle
Schnittstelle mit TIA-/EIA-232 Pegeln gebaut. Der Prozessor implementiert das
Schnittstelle mit TIA-/EIA-232 Pegeln gewählt. Der Prozessor implementiert das
RISC-V32I base instruction set. Aufgrund der starken Verwendung von Englisch im
Software- und Hardwarebereich wurde diese Diplomarbeit in Englisch verfasst, was
ebenfalls die Lesbarkeit erhöhen soll. Die entstandene Dokumentation soll für
Menschen mit einem Grundlegenden Verständnis von Elektronik sowie der Hardware-
Menschen mit einem grundlegenden Verständnis von Elektronik sowie der Hardware-
Beschreibungssprache VHDL verständlich sein.
\end{otherlanguage}
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This diploma thesis deals with the operation of processors and their
orresponding peripherials in modern andd traditional forms. It attempts to
corresponding peripherials in modern and traditional forms. It attempts to
illustrate the structure of a computersystem in hard- and software. To reach
this goal a RISC-V32I processor has been implemented in VHDL on a XILINX FPGA
as well as some peripherials bound to the parallel bus. These peripherials