dipl/sections/core/entities/memctl_entity.vhd

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2020-03-27 12:51:39 +01:00
entity memctl is
port (
addr : in yarm_word;
-- data width
data_width : in datum_width_t;
-- perfom sign extension when reading short data
sign_extend : in std_logic;
data_read : out yarm_word;
data_write : in yarm_word;
MEM_addr : out yarm_word;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word
);
end memctl;