splink/vhdl/splink.vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity splink is
	generic (
		NUM_STRANDS : positive;
		MAX_STRAND_LEN : positive := 256
	);
	port (
		clk : in std_logic;
		reset : in std_logic;

		drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
	);
end entity;

architecture a of splink is
	signal driver_out : std_logic;
begin
	ws2812_inst: entity work.ws2812
		generic map (
			NUM_LEDS => 20,
			COLOR_ORDER => "GRB",
			T_CLK => 12.5 ns,

			T0H => 0.35 us,
			T0L => 0.8 us,
			T1H => 0.7 us,
			T1L => 0.6 us,

			T_RES => 80 us
		)
		port map (
			n_reset => not reset,
			clk     => clk,

			led_addr => open,

			led_red   => x"ff",
			led_green => x"00",
			led_blue  => x"ff",

			dout => driver_out
		);

	-- https://github.com/YosysHQ/yosys/issues/3360
	drivers <= (19 => driver_out, others => '0');
end architecture;