xiretza/splink
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base: xiretza:bad48d0e9bc3f7755fba621f08ed606ce74273a1
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xiretza:liteeth-wishbone
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compare: xiretza:4d07ec3fa1b2259dd585f91a892bbdbf6cea4e4a
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2 changed files with 31 additions and 74 deletions
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53
vhdl/arty_a7.vhdl
View file

@ -2,8 +2,6 @@ library ieee;
use ieee.std_logic_1164.all, use ieee.std_logic_1164.all,
ieee.numeric_std.all; ieee.numeric_std.all;
use work.util.flip_endianness;
entity arty_a7 is entity arty_a7 is
generic ( generic (
IS_SIMULATION : std_logic := '0' IS_SIMULATION : std_logic := '0'
@ -192,13 +190,7 @@ architecture a of arty_a7 is
signal sys_reset : std_logic; signal sys_reset : std_logic;
signal frame_number : unsigned(31 downto 0); signal frame_done : std_logic;
signal prev_frame_number : unsigned(31 downto 0);
-- little-endian pixel sink data
signal pixel_sink_data_le : std_logic_vector(31 downto 0);
-- big-endian pixel source data
signal pixel_source_data_be : std_logic_vector(31 downto 0);
begin begin
leds_simple <= (others => '0'); leds_simple <= (others => '0');
led0 <= (others => '0'); led0 <= (others => '0');
@ -249,7 +241,7 @@ begin
pixel_sink_last => pixel_sink_last, pixel_sink_last => pixel_sink_last,
pixel_sink_last_be => pixel_sink_last_be, pixel_sink_last_be => pixel_sink_last_be,
pixel_sink_ready => pixel_sink_ready, pixel_sink_ready => pixel_sink_ready,
pixel_sink_data => pixel_sink_data_le, pixel_sink_data => pixel_sink_data,
-- source -- source
pixel_source_src_ip_address => pixel_source_src_ip_address, pixel_source_src_ip_address => pixel_source_src_ip_address,
@ -262,7 +254,6 @@ begin
pixel_source_ready => '1', pixel_source_ready => '1',
pixel_source_data => pixel_source_data pixel_source_data => pixel_source_data
); );
pixel_sink_data_le <= flip_endianness(pixel_sink_data);
-- 800 MHz VCO -- 800 MHz VCO
-- 80 MHz system clock -- 80 MHz system clock
@ -308,28 +299,27 @@ begin
pmod_d <= drivers(23 downto 16); pmod_d <= drivers(23 downto 16);
sender: process(sys_clk) sender: process(sys_clk)
variable frame_counter : unsigned(31 downto 0);
begin begin
if rising_edge(sys_clk) then if sys_reset then
if sys_reset then frame_counter := (others => '0');
prev_frame_number <= frame_number; elsif rising_edge(sys_clk) then
else if pixel_source_valid then
if pixel_source_valid then remote_ip_address <= pixel_source_src_ip_address;
remote_ip_address <= pixel_source_src_ip_address; remote_port <= pixel_source_src_port;
remote_port <= pixel_source_src_port; end if;
end if;
if frame_number /= prev_frame_number then if frame_done then
prev_frame_number <= frame_number; pixel_sink_length <= x"0004";
pixel_sink_data <= std_logic_vector(frame_counter);
pixel_sink_valid <= '1';
pixel_sink_last <= '1';
pixel_sink_length <= x"0004"; frame_counter := frame_counter + 1;
pixel_sink_data <= std_logic_vector(frame_number); end if;
pixel_sink_valid <= '1';
pixel_sink_last <= '1';
end if;
if pixel_sink_ready and pixel_sink_valid then if pixel_sink_ready and pixel_sink_valid then
pixel_sink_valid <= '0'; pixel_sink_valid <= '0';
end if;
end if; end if;
end if; end if;
end process; end process;
@ -345,11 +335,10 @@ begin
udp_valid => pixel_source_valid, udp_valid => pixel_source_valid,
udp_last => pixel_source_last, udp_last => pixel_source_last,
udp_data => pixel_source_data_be, udp_data => pixel_source_data,
frame_number => frame_number, frame_done => frame_done,
drivers => drivers drivers => drivers
); );
pixel_source_data_be <= flip_endianness(pixel_source_data);
end architecture; end architecture;

52
vhdl/splink.vhdl
View file

@ -15,7 +15,7 @@ entity splink is
udp_last : in std_logic; udp_last : in std_logic;
udp_data : in std_logic_vector(31 downto 0); udp_data : in std_logic_vector(31 downto 0);
frame_number : out unsigned(31 downto 0); frame_done : out std_logic;
drivers : out std_logic_vector(NUM_STRANDS-1 downto 0) drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
); );
@ -37,19 +37,10 @@ architecture a of splink is
signal active_strand: natural range 0 to NUM_STRANDS-1; signal active_strand: natural range 0 to NUM_STRANDS-1;
signal num_pixels: natural range 1 to MAX_STRAND_LEN; signal num_pixels: natural range 1 to MAX_STRAND_LEN;
signal current_frame: unsigned(31 downto 0); signal frame_number: unsigned(31 downto 0);
signal pixels_received: natural range 0 to MAX_STRAND_LEN-1; signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
signal clear_write_flags : std_logic; type receive_state_t is (FRAME_NUM, STRAND_NUM, DATA, DROP);
signal all_strands_written : std_logic;
signal some_strands_written : std_logic;
-- "PIXL"
constant MAGIC_NUMBER : std_logic_vector(31 downto 0) := x"5049584c";
type receive_state_t is (MAGIC, FRAME_NUM, STRAND_NUM, DATA, DROP);
constant RESET_STATE : receive_state_t := MAGIC;
signal receive_state : receive_state_t; signal receive_state : receive_state_t;
begin begin
driver_gen: for i in 0 to NUM_STRANDS-1 generate driver_gen: for i in 0 to NUM_STRANDS-1 generate
@ -94,7 +85,7 @@ begin
end if; end if;
end if; end if;
if clear_write_flags then if frame_done then
led_data_arr(i).was_written <= '0'; led_data_arr(i).was_written <= '0';
end if; end if;
end if; end if;
@ -103,14 +94,11 @@ begin
process(led_data_arr) process(led_data_arr)
begin begin
all_strands_written <= '1'; frame_done <= '1';
some_strands_written <= '0';
for i in 0 to NUM_STRANDS-1 loop for i in 0 to NUM_STRANDS-1 loop
if led_data_arr(i).was_written then if not led_data_arr(i).was_written then
some_strands_written <= '1'; frame_done <= '0';
else
all_strands_written <= '0';
end if; end if;
end loop; end loop;
end process; end process;
@ -118,30 +106,15 @@ begin
fsm: process(clk) fsm: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
clear_write_flags <= '0';
if all_strands_written then
frame_number <= current_frame;
clear_write_flags <= '1';
end if;
if reset then if reset then
clear_write_flags <= '1'; receive_state <= STRAND_NUM;
receive_state <= RESET_STATE;
elsif udp_valid then elsif udp_valid then
if udp_last then if udp_last then
-- always resynchronize to start of packet -- always resynchronize to start of packet
receive_state <= RESET_STATE; receive_state <= STRAND_NUM;
end if; end if;
case receive_state is case receive_state is
when MAGIC =>
if udp_data = MAGIC_NUMBER then
receive_state <= STRAND_NUM;
else
receive_state <= DROP;
end if;
when STRAND_NUM => when STRAND_NUM =>
-- TODO udp_length, range check with MAX_STRAND_LEN -- TODO udp_length, range check with MAX_STRAND_LEN
num_pixels <= MAX_STRAND_LEN; num_pixels <= MAX_STRAND_LEN;
@ -152,12 +125,7 @@ begin
receive_state <= FRAME_NUM; receive_state <= FRAME_NUM;
when FRAME_NUM => when FRAME_NUM =>
if not some_strands_written then frame_number <= unsigned(udp_data);
current_frame <= unsigned(udp_data);
elsif current_frame /= unsigned(udp_data) then
current_frame <= unsigned(udp_data);
clear_write_flags <= '1';
end if;
pixels_received <= 0; pixels_received <= 0;
receive_state <= DATA; receive_state <= DATA;