vhdl/arty_a7.vhdl

@@ -2,8 +2,6 @@ library ieee;
 use ieee.std_logic_1164.all,
     ieee.numeric_std.all;
 
-use work.util.flip_endianness;
-
 entity arty_a7 is
 	generic (
 		IS_SIMULATION : std_logic := '0'
@@ -192,13 +190,7 @@ architecture a of arty_a7 is
 
 	signal sys_reset : std_logic;
 
-	signal frame_number : unsigned(31 downto 0);
-	signal prev_frame_number : unsigned(31 downto 0);
-
-	-- little-endian pixel sink data
-	signal pixel_sink_data_le : std_logic_vector(31 downto 0);
-	-- big-endian pixel source data
-	signal pixel_source_data_be : std_logic_vector(31 downto 0);
+	signal frame_done : std_logic;
 begin
 	leds_simple <= (others => '0');
 	led0 <= (others => '0');
@@ -249,7 +241,7 @@ begin
 		pixel_sink_last => pixel_sink_last,
 		pixel_sink_last_be => pixel_sink_last_be,
 		pixel_sink_ready => pixel_sink_ready,
-		pixel_sink_data => pixel_sink_data_le,
+		pixel_sink_data => pixel_sink_data,
 
 		-- source
 		pixel_source_src_ip_address => pixel_source_src_ip_address,
@@ -262,7 +254,6 @@ begin
 		pixel_source_ready => '1',
 		pixel_source_data => pixel_source_data
 	);
-	pixel_sink_data_le <= flip_endianness(pixel_sink_data);
 
 	-- 800 MHz VCO
 	-- 80 MHz system clock
@@ -308,28 +299,27 @@ begin
 	pmod_d <= drivers(23 downto 16);
 
 	sender: process(sys_clk)
+		variable frame_counter : unsigned(31 downto 0);
 	begin
-		if rising_edge(sys_clk) then
-			if sys_reset then
-				prev_frame_number <= frame_number;
-			else
-				if pixel_source_valid then
-					remote_ip_address <= pixel_source_src_ip_address;
-					remote_port <= pixel_source_src_port;
-				end if;
+		if sys_reset then
+			frame_counter := (others => '0');
+		elsif rising_edge(sys_clk) then
+			if pixel_source_valid then
+				remote_ip_address <= pixel_source_src_ip_address;
+				remote_port <= pixel_source_src_port;
+			end if;
 
-				if frame_number /= prev_frame_number then
-					prev_frame_number <= frame_number;
+			if frame_done then
+				pixel_sink_length <= x"0004";
+				pixel_sink_data <= std_logic_vector(frame_counter);
+				pixel_sink_valid <= '1';
+				pixel_sink_last <= '1';
 
-					pixel_sink_length <= x"0004";
-					pixel_sink_data <= std_logic_vector(frame_number);
-					pixel_sink_valid <= '1';
-					pixel_sink_last <= '1';
-				end if;
+				frame_counter := frame_counter + 1;
+			end if;
 
-				if pixel_sink_ready and pixel_sink_valid then
-					pixel_sink_valid <= '0';
-				end if;
+			if pixel_sink_ready and pixel_sink_valid then
+				pixel_sink_valid <= '0';
 			end if;
 		end if;
 	end process;
@@ -345,11 +335,10 @@ begin
 
 			udp_valid => pixel_source_valid,
 			udp_last => pixel_source_last,
-			udp_data => pixel_source_data_be,
+			udp_data => pixel_source_data,
 
-			frame_number => frame_number,
+			frame_done => frame_done,
 
 			drivers => drivers
 		);
-	pixel_source_data_be <= flip_endianness(pixel_source_data);
 end architecture;

vhdl/splink.vhdl

@@ -15,7 +15,7 @@ entity splink is
 		udp_last : in std_logic;
 		udp_data : in std_logic_vector(31 downto 0);
 
-		frame_number : out unsigned(31 downto 0);
+		frame_done : out std_logic;
 
 		drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
 	);
@@ -37,19 +37,10 @@ architecture a of splink is
 
 	signal active_strand: natural range 0 to NUM_STRANDS-1;
 	signal num_pixels: natural range 1 to MAX_STRAND_LEN;
-	signal current_frame: unsigned(31 downto 0);
+	signal frame_number: unsigned(31 downto 0);
 	signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
 
-	signal clear_write_flags : std_logic;
-
-	signal all_strands_written : std_logic;
-	signal some_strands_written : std_logic;
-
-	-- "PIXL"
-	constant MAGIC_NUMBER : std_logic_vector(31 downto 0) := x"5049584c";
-
-	type receive_state_t is (MAGIC, FRAME_NUM, STRAND_NUM, DATA, DROP);
-	constant RESET_STATE : receive_state_t := MAGIC;
+	type receive_state_t is (FRAME_NUM, STRAND_NUM, DATA, DROP);
 	signal receive_state : receive_state_t;
 begin
 	driver_gen: for i in 0 to NUM_STRANDS-1 generate
@@ -94,7 +85,7 @@ begin
 					end if;
 				end if;
 
-				if clear_write_flags then
+				if frame_done then
 					led_data_arr(i).was_written <= '0';
 				end if;
 			end if;
@@ -103,14 +94,11 @@ begin
 
 	process(led_data_arr)
 	begin
-		all_strands_written <= '1';
-		some_strands_written <= '0';
+		frame_done <= '1';
 
 		for i in 0 to NUM_STRANDS-1 loop
-			if led_data_arr(i).was_written then
-				some_strands_written <= '1';
-			else
-				all_strands_written <= '0';
+			if not led_data_arr(i).was_written then
+				frame_done <= '0';
 			end if;
 		end loop;
 	end process;
@@ -118,30 +106,15 @@ begin
 	fsm: process(clk)
 	begin
 		if rising_edge(clk) then
-			clear_write_flags <= '0';
-
-			if all_strands_written then
-				frame_number <= current_frame;
-				clear_write_flags <= '1';
-			end if;
-
 			if reset then
-				clear_write_flags <= '1';
-				receive_state <= RESET_STATE;
+				receive_state <= STRAND_NUM;
 			elsif udp_valid then
 				if udp_last then
 					-- always resynchronize to start of packet
-					receive_state <= RESET_STATE;
+					receive_state <= STRAND_NUM;
 				end if;
 
 				case receive_state is
-					when MAGIC =>
-						if udp_data = MAGIC_NUMBER then
-							receive_state <= STRAND_NUM;
-						else
-							receive_state <= DROP;
-						end if;
-
 					when STRAND_NUM =>
 						-- TODO udp_length, range check with MAX_STRAND_LEN
 						num_pixels <= MAX_STRAND_LEN;
@@ -152,12 +125,7 @@ begin
 						receive_state <= FRAME_NUM;
 
 					when FRAME_NUM =>
-						if not some_strands_written then
-							current_frame <= unsigned(udp_data);
-						elsif current_frame /= unsigned(udp_data) then
-							current_frame <= unsigned(udp_data);
-							clear_write_flags <= '1';
-						end if;
+						frame_number <= unsigned(udp_data);
 
 						pixels_received <= 0;
 						receive_state <= DATA;