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vhdl: remove unused signals

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Xiretza 2022-06-05 22:26:24 +02:00
parent 79fce1afc1
commit d0e65a3126
2 changed files with 3 additions and 20 deletions
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15
vhdl/arty_a7.vhdl
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@ -119,11 +119,8 @@ architecture a of arty_a7 is
signal pixel_source_src_ip_address : std_logic_vector(31 downto 0); signal pixel_source_src_ip_address : std_logic_vector(31 downto 0);
signal pixel_source_src_port : std_logic_vector(15 downto 0); signal pixel_source_src_port : std_logic_vector(15 downto 0);
signal pixel_source_length : std_logic_vector(15 downto 0);
signal pixel_source_valid : std_logic; signal pixel_source_valid : std_logic;
signal pixel_source_last : std_logic; signal pixel_source_last : std_logic;
signal pixel_source_last_be : std_logic_vector(3 downto 0);
signal pixel_source_ready : std_logic;
signal pixel_source_data : std_logic_vector(31 downto 0); signal pixel_source_data : std_logic_vector(31 downto 0);
component PLLE2_BASE component PLLE2_BASE
@ -245,11 +242,11 @@ begin
pixel_source_src_ip_address => pixel_source_src_ip_address, pixel_source_src_ip_address => pixel_source_src_ip_address,
pixel_source_src_port => pixel_source_src_port, pixel_source_src_port => pixel_source_src_port,
pixel_source_length => pixel_source_length, pixel_source_length => open,
pixel_source_valid => pixel_source_valid, pixel_source_valid => pixel_source_valid,
pixel_source_last => pixel_source_last, pixel_source_last => pixel_source_last,
pixel_source_last_be => pixel_source_last_be, pixel_source_last_be => open,
pixel_source_ready => pixel_source_ready, pixel_source_ready => '1',
pixel_source_data => pixel_source_data pixel_source_data => pixel_source_data
); );
@ -333,14 +330,8 @@ begin
clk => sys_clk, clk => sys_clk,
reset => sys_reset, reset => sys_reset,
udp_src_ip_address => pixel_source_src_ip_address,
udp_src_port => pixel_source_src_port,
udp_length => pixel_source_length,
udp_valid => pixel_source_valid, udp_valid => pixel_source_valid,
udp_last => pixel_source_last, udp_last => pixel_source_last,
udp_last_be => pixel_source_last_be,
udp_ready => pixel_source_ready,
udp_data => pixel_source_data, udp_data => pixel_source_data,
drivers => drivers drivers => drivers

8
vhdl/splink.vhdl
View file

@ -11,14 +11,8 @@ entity splink is
clk : in std_logic; clk : in std_logic;
reset : in std_logic; reset : in std_logic;
udp_src_ip_address : in std_logic_vector(31 downto 0);
udp_src_port : in std_logic_vector(15 downto 0);
udp_length : in std_logic_vector(15 downto 0);
udp_valid : in std_logic; udp_valid : in std_logic;
udp_last : in std_logic; udp_last : in std_logic;
udp_last_be : in std_logic_vector(3 downto 0);
udp_ready : out std_logic;
udp_data : in std_logic_vector(31 downto 0); udp_data : in std_logic_vector(31 downto 0);
drivers : out std_logic_vector(NUM_STRANDS-1 downto 0) drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
@ -82,6 +76,4 @@ begin
end if; end if;
end if; end if;
end process; end process;
udp_ready <= '1';
end architecture; end architecture;