diff --git a/vhdl/arty_a7.vhdl b/vhdl/arty_a7.vhdl
index 933b5ff..1057e84 100644
--- a/vhdl/arty_a7.vhdl
+++ b/vhdl/arty_a7.vhdl
@@ -119,11 +119,8 @@ architecture a of arty_a7 is
 	signal pixel_source_src_ip_address : std_logic_vector(31 downto 0);
 	signal pixel_source_src_port : std_logic_vector(15 downto 0);
 
-	signal pixel_source_length : std_logic_vector(15 downto 0);
 	signal pixel_source_valid : std_logic;
 	signal pixel_source_last : std_logic;
-	signal pixel_source_last_be : std_logic_vector(3 downto 0);
-	signal pixel_source_ready : std_logic;
 	signal pixel_source_data : std_logic_vector(31 downto 0);
 
 	component PLLE2_BASE
@@ -245,11 +242,11 @@ begin
 		pixel_source_src_ip_address => pixel_source_src_ip_address,
 		pixel_source_src_port => pixel_source_src_port,
 
-		pixel_source_length => pixel_source_length,
+		pixel_source_length => open,
 		pixel_source_valid => pixel_source_valid,
 		pixel_source_last => pixel_source_last,
-		pixel_source_last_be => pixel_source_last_be,
-		pixel_source_ready => pixel_source_ready,
+		pixel_source_last_be => open,
+		pixel_source_ready => '1',
 		pixel_source_data => pixel_source_data
 	);
 
@@ -333,14 +330,8 @@ begin
 			clk => sys_clk,
 			reset => sys_reset,
 
-			udp_src_ip_address => pixel_source_src_ip_address,
-			udp_src_port => pixel_source_src_port,
-
-			udp_length => pixel_source_length,
 			udp_valid => pixel_source_valid,
 			udp_last => pixel_source_last,
-			udp_last_be => pixel_source_last_be,
-			udp_ready => pixel_source_ready,
 			udp_data => pixel_source_data,
 
 			drivers => drivers
diff --git a/vhdl/splink.vhdl b/vhdl/splink.vhdl
index 81f6e69..426ab9d 100644
--- a/vhdl/splink.vhdl
+++ b/vhdl/splink.vhdl
@@ -11,14 +11,8 @@ entity splink is
 		clk : in std_logic;
 		reset : in std_logic;
 
-		udp_src_ip_address : in std_logic_vector(31 downto 0);
-		udp_src_port : in std_logic_vector(15 downto 0);
-
-		udp_length : in std_logic_vector(15 downto 0);
 		udp_valid : in std_logic;
 		udp_last : in std_logic;
-		udp_last_be : in std_logic_vector(3 downto 0);
-		udp_ready : out std_logic;
 		udp_data : in std_logic_vector(31 downto 0);
 
 		drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
@@ -82,6 +76,4 @@ begin
 			end if;
 		end if;
 	end process;
-
-	udp_ready <= '1';
 end architecture;