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vhdl: implement feedback packets

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Xiretza 2022-06-05 22:56:29 +02:00
parent d0e65a3126
commit ccd911dc1e
2 changed files with 31 additions and 22 deletions
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51
vhdl/arty_a7.vhdl
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@ -123,6 +123,9 @@ architecture a of arty_a7 is
signal pixel_source_last : std_logic;
signal pixel_source_data : std_logic_vector(31 downto 0);
signal remote_ip_address : std_logic_vector(31 downto 0);
signal remote_port : std_logic_vector(15 downto 0);
component PLLE2_BASE
generic (
CLKFBOUT_MULT : integer;
@ -186,6 +189,8 @@ architecture a of arty_a7 is
end component BUFG;
signal sys_reset : std_logic;
signal frame_done : std_logic;
begin
leds_simple <= (others => '0');
led0 <= (others => '0');
@ -228,8 +233,8 @@ begin
pixel_bind_port => x"effd", -- port 61437 - "PIXEL"
-- sink
pixel_sink_dst_ip_address => x"0a141e29",
pixel_sink_dst_port => x"303a", -- port 12346
pixel_sink_dst_ip_address => remote_ip_address,
pixel_sink_dst_port => remote_port,
pixel_sink_length => pixel_sink_length,
pixel_sink_valid => pixel_sink_valid,
@ -294,29 +299,27 @@ begin
pmod_d <= drivers(23 downto 16);
sender: process(sys_clk)
constant COUNTER_MAX: natural := 80000000;
variable counter: natural range 0 to COUNTER_MAX;
constant NUM_WORDS: natural := 10;
variable words_sent: natural range 0 to NUM_WORDS;
variable frame_counter : unsigned(31 downto 0);
begin
if rising_edge(sys_clk) then
if counter = COUNTER_MAX then
pixel_sink_length <= std_logic_vector(to_unsigned(NUM_WORDS, 16));
pixel_sink_data <= std_logic_vector(to_unsigned(16#30# + words_sent, 32));
--pixel_sink_valid <= '1';
pixel_sink_last <= '1' when words_sent = NUM_WORDS-1 else '0';
if words_sent = NUM_WORDS then
pixel_sink_valid <= '0';
counter := 0;
words_sent := 0;
elsif pixel_sink_ready then
words_sent := words_sent + 1;
if sys_reset then
frame_counter := (others => '0');
elsif rising_edge(sys_clk) then
if pixel_source_valid then
remote_ip_address <= pixel_source_src_ip_address;
remote_port <= pixel_source_src_port;
end if;
else
counter := counter + 1;
if frame_done then
pixel_sink_length <= x"0004";
pixel_sink_data <= std_logic_vector(frame_counter);
pixel_sink_valid <= '1';
pixel_sink_last <= '1';
frame_counter := frame_counter + 1;
end if;
if pixel_sink_ready and pixel_sink_valid then
pixel_sink_valid <= '0';
end if;
end if;
end process;
@ -334,6 +337,8 @@ begin
udp_last => pixel_source_last,
udp_data => pixel_source_data,
frame_done => frame_done,
drivers => drivers
);
end architecture;

4
vhdl/splink.vhdl
View file

@ -15,6 +15,8 @@ entity splink is
udp_last : in std_logic;
udp_data : in std_logic_vector(31 downto 0);
frame_done : out std_logic;
drivers : out std_logic_vector(NUM_STRANDS-1 downto 0)
);
end entity;
@ -63,12 +65,14 @@ begin
variable store_counter: natural range 0 to MAX_STRAND_LEN-1;
begin
if rising_edge(clk) then
frame_done <= '0';
current_color <= strand_store(to_integer(unsigned(led_addr)));
if udp_valid then
strand_store(store_counter) <= udp_data(23 downto 0);
if udp_last then
frame_done <= '1';
store_counter := 0;
elsif store_counter /= MAX_STRAND_LEN-1 then
store_counter := store_counter + 1;