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vhdl: only run encoders once all pixels are received

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Xiretza 2022-06-06 18:38:56 +02:00
parent 9ca64a7d4d
commit 70a7b0520a
1 changed files with 4 additions and 0 deletions
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vhdl/splink.vhdl
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@ -40,6 +40,7 @@ architecture a of splink is
signal current_frame: unsigned(31 downto 0); signal current_frame: unsigned(31 downto 0);
signal pixels_received: natural range 0 to MAX_STRAND_LEN-1; signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
signal run : std_logic;
signal clear_write_flags : std_logic; signal clear_write_flags : std_logic;
signal all_strands_written : std_logic; signal all_strands_written : std_logic;
@ -69,6 +70,7 @@ begin
port map ( port map (
n_reset => not reset, n_reset => not reset,
clk => clk, clk => clk,
run => run,
led_addr => led_data_arr(i).addr, led_addr => led_data_arr(i).addr,
@ -119,10 +121,12 @@ begin
begin begin
if rising_edge(clk) then if rising_edge(clk) then
clear_write_flags <= '0'; clear_write_flags <= '0';
run <= '0';
if all_strands_written then if all_strands_written then
frame_number <= current_frame; frame_number <= current_frame;
clear_write_flags <= '1'; clear_write_flags <= '1';
run <= '1';
end if; end if;
if reset then if reset then