From 70a7b0520aa930362a720f2afd24d178da9f39f5 Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Mon, 6 Jun 2022 18:38:56 +0200
Subject: [PATCH] vhdl: only run encoders once all pixels are received

---
 vhdl/splink.vhdl | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/vhdl/splink.vhdl b/vhdl/splink.vhdl
index ccd3062..c470658 100644
--- a/vhdl/splink.vhdl
+++ b/vhdl/splink.vhdl
@@ -40,6 +40,7 @@ architecture a of splink is
 	signal current_frame: unsigned(31 downto 0);
 	signal pixels_received: natural range 0 to MAX_STRAND_LEN-1;
 
+	signal run : std_logic;
 	signal clear_write_flags : std_logic;
 
 	signal all_strands_written : std_logic;
@@ -69,6 +70,7 @@ begin
 			port map (
 				n_reset => not reset,
 				clk     => clk,
+				run     => run,
 
 				led_addr => led_data_arr(i).addr,
 
@@ -119,10 +121,12 @@ begin
 	begin
 		if rising_edge(clk) then
 			clear_write_flags <= '0';
+			run <= '0';
 
 			if all_strands_written then
 				frame_number <= current_frame;
 				clear_write_flags <= '1';
+				run <= '1';
 			end if;
 
 			if reset then