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vhdl: use UDP packet length

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Xiretza 2022-06-06 18:42:37 +02:00
parent 70a7b0520a
commit 645a838a73
2 changed files with 14 additions and 7 deletions
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4
vhdl/arty_a7.vhdl
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@ -121,6 +121,7 @@ architecture a of arty_a7 is
signal pixel_source_src_ip_address : std_logic_vector(31 downto 0); signal pixel_source_src_ip_address : std_logic_vector(31 downto 0);
signal pixel_source_src_port : std_logic_vector(15 downto 0); signal pixel_source_src_port : std_logic_vector(15 downto 0);
signal pixel_source_length : std_logic_vector(15 downto 0);
signal pixel_source_valid : std_logic; signal pixel_source_valid : std_logic;
signal pixel_source_last : std_logic; signal pixel_source_last : std_logic;
signal pixel_source_data : std_logic_vector(31 downto 0); signal pixel_source_data : std_logic_vector(31 downto 0);
@ -255,7 +256,7 @@ begin
pixel_source_src_ip_address => pixel_source_src_ip_address, pixel_source_src_ip_address => pixel_source_src_ip_address,
pixel_source_src_port => pixel_source_src_port, pixel_source_src_port => pixel_source_src_port,
pixel_source_length => open, pixel_source_length => pixel_source_length,
pixel_source_valid => pixel_source_valid, pixel_source_valid => pixel_source_valid,
pixel_source_last => pixel_source_last, pixel_source_last => pixel_source_last,
pixel_source_last_be => open, pixel_source_last_be => open,
@ -343,6 +344,7 @@ begin
clk => sys_clk, clk => sys_clk,
reset => sys_reset, reset => sys_reset,
udp_length => pixel_source_length,
udp_valid => pixel_source_valid, udp_valid => pixel_source_valid,
udp_last => pixel_source_last, udp_last => pixel_source_last,
udp_data => pixel_source_data_be, udp_data => pixel_source_data_be,

17
vhdl/splink.vhdl
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@ -11,6 +11,7 @@ entity splink is
clk : in std_logic; clk : in std_logic;
reset : in std_logic; reset : in std_logic;
udp_length : in std_logic_vector(15 downto 0);
udp_valid : in std_logic; udp_valid : in std_logic;
udp_last : in std_logic; udp_last : in std_logic;
udp_data : in std_logic_vector(31 downto 0); udp_data : in std_logic_vector(31 downto 0);
@ -48,6 +49,8 @@ architecture a of splink is
-- "PIXL" -- "PIXL"
constant MAGIC_NUMBER : std_logic_vector(31 downto 0) := x"5049584c"; constant MAGIC_NUMBER : std_logic_vector(31 downto 0) := x"5049584c";
-- magic + frame num + strand num (4 bytes each)
constant HEADER_LEN : natural := 12;
type receive_state_t is (MAGIC, FRAME_NUM, STRAND_NUM, DATA, DROP); type receive_state_t is (MAGIC, FRAME_NUM, STRAND_NUM, DATA, DROP);
constant RESET_STATE : receive_state_t := MAGIC; constant RESET_STATE : receive_state_t := MAGIC;
@ -140,16 +143,18 @@ begin
case receive_state is case receive_state is
when MAGIC => when MAGIC =>
if udp_data = MAGIC_NUMBER then if udp_data /= MAGIC_NUMBER then
receive_state <= STRAND_NUM;
else
receive_state <= DROP; receive_state <= DROP;
else
if (unsigned(udp_length) - HEADER_LEN) / 4 > MAX_STRAND_LEN then
receive_state <= DROP;
else
num_pixels <= (to_integer(unsigned(udp_length)) - HEADER_LEN) / 4;
receive_state <= STRAND_NUM;
end if;
end if; end if;
when STRAND_NUM => when STRAND_NUM =>
-- TODO udp_length, range check with MAX_STRAND_LEN
num_pixels <= MAX_STRAND_LEN;
if unsigned(udp_data) >= NUM_STRANDS then if unsigned(udp_data) >= NUM_STRANDS then
receive_state <= DROP; receive_state <= DROP;
else else