vhdl: move ws2812 driver to splink module
This commit is contained in:
parent
94ff182aec
commit
57e6daedcc
2 changed files with 37 additions and 57 deletions
|
@ -16,8 +16,8 @@ entity arty_a7 is
|
||||||
-- Pmod connectors - A+D standard, B+C high-speed.
|
-- Pmod connectors - A+D standard, B+C high-speed.
|
||||||
-- Defined as inputs by default for safety, change
|
-- Defined as inputs by default for safety, change
|
||||||
-- when necessary
|
-- when necessary
|
||||||
pmod_a : in std_logic_vector(7 downto 0);
|
pmod_a : out std_logic_vector(7 downto 0);
|
||||||
pmod_b : in std_logic_vector(7 downto 0);
|
pmod_b : out std_logic_vector(7 downto 0);
|
||||||
pmod_c : in std_logic_vector(7 downto 0);
|
pmod_c : in std_logic_vector(7 downto 0);
|
||||||
pmod_d : out std_logic_vector(7 downto 0);
|
pmod_d : out std_logic_vector(7 downto 0);
|
||||||
|
|
||||||
|
@ -46,7 +46,7 @@ entity arty_a7 is
|
||||||
end arty_a7;
|
end arty_a7;
|
||||||
|
|
||||||
architecture a of arty_a7 is
|
architecture a of arty_a7 is
|
||||||
constant NUM_DRIVERS: positive := 16;
|
constant NUM_DRIVERS: positive := 24;
|
||||||
signal drivers: std_logic_vector(NUM_DRIVERS-1 downto 0);
|
signal drivers: std_logic_vector(NUM_DRIVERS-1 downto 0);
|
||||||
|
|
||||||
component liteeth_core is
|
component liteeth_core is
|
||||||
|
@ -180,7 +180,7 @@ architecture a of arty_a7 is
|
||||||
|
|
||||||
signal sys_reset : std_logic;
|
signal sys_reset : std_logic;
|
||||||
begin
|
begin
|
||||||
--leds_simple <= (others => '0');
|
leds_simple <= (others => '0');
|
||||||
led0 <= (others => '0');
|
led0 <= (others => '0');
|
||||||
led1 <= (others => '0');
|
led1 <= (others => '0');
|
||||||
led2 <= (others => '0');
|
led2 <= (others => '0');
|
||||||
|
@ -191,8 +191,6 @@ begin
|
||||||
ck_dig_l <= (others => 'Z');
|
ck_dig_l <= (others => 'Z');
|
||||||
ck_dig_h <= (others => 'Z');
|
ck_dig_h <= (others => 'Z');
|
||||||
|
|
||||||
leds_simple <= drivers(3 downto 0);
|
|
||||||
|
|
||||||
liteeth_inst: liteeth_core port map (
|
liteeth_inst: liteeth_core port map (
|
||||||
sys_clock => clk_sys,
|
sys_clock => clk_sys,
|
||||||
sys_reset => sys_reset,
|
sys_reset => sys_reset,
|
||||||
|
@ -284,40 +282,9 @@ begin
|
||||||
|
|
||||||
sys_reset <= not pll_locked or not n_reset;
|
sys_reset <= not pll_locked or not n_reset;
|
||||||
|
|
||||||
ws2812_inst: entity work.ws2812
|
pmod_a <= drivers(7 downto 0);
|
||||||
generic map (
|
pmod_b <= drivers(15 downto 8);
|
||||||
NUM_LEDS => 20,
|
pmod_d <= drivers(23 downto 16);
|
||||||
COLOR_ORDER => "GRB",
|
|
||||||
T_CLK => 12.5 ns,
|
|
||||||
|
|
||||||
T0H => 0.35 us,
|
|
||||||
T0L => 0.8 us,
|
|
||||||
T1H => 0.7 us,
|
|
||||||
T1L => 0.6 us,
|
|
||||||
|
|
||||||
T_RES => 80 us
|
|
||||||
)
|
|
||||||
port map (
|
|
||||||
n_reset => not sys_reset,
|
|
||||||
clk => clk_sys,
|
|
||||||
|
|
||||||
led_addr => open,
|
|
||||||
|
|
||||||
led_red => x"ff",
|
|
||||||
led_green => x"00",
|
|
||||||
led_blue => x"ff",
|
|
||||||
|
|
||||||
dout => pmod_d(3)
|
|
||||||
);
|
|
||||||
|
|
||||||
-- https://github.com/YosysHQ/yosys/issues/3360
|
|
||||||
pmod_d(0) <= '0';
|
|
||||||
pmod_d(1) <= '0';
|
|
||||||
pmod_d(2) <= '0';
|
|
||||||
pmod_d(4) <= '0';
|
|
||||||
pmod_d(5) <= '0';
|
|
||||||
pmod_d(6) <= '0';
|
|
||||||
pmod_d(7) <= '0';
|
|
||||||
|
|
||||||
sender: process(clk_sys)
|
sender: process(clk_sys)
|
||||||
constant COUNTER_MAX: natural := 80000000;
|
constant COUNTER_MAX: natural := 80000000;
|
||||||
|
|
|
@ -4,9 +4,8 @@ use ieee.numeric_std.all;
|
||||||
|
|
||||||
entity splink is
|
entity splink is
|
||||||
generic (
|
generic (
|
||||||
NUM_DRIVERS : positive := 16;
|
NUM_DRIVERS : positive;
|
||||||
ROWS : positive := 100;
|
MAX_STRAND_LEN : positive := 256
|
||||||
COLS : positive := 100
|
|
||||||
);
|
);
|
||||||
port (
|
port (
|
||||||
clk : in std_logic;
|
clk : in std_logic;
|
||||||
|
@ -17,20 +16,34 @@ entity splink is
|
||||||
end entity;
|
end entity;
|
||||||
|
|
||||||
architecture a of splink is
|
architecture a of splink is
|
||||||
signal count2: unsigned(3 downto 0);
|
signal driver_out : std_logic;
|
||||||
signal count: natural range 0 to 10000000;
|
|
||||||
begin
|
begin
|
||||||
process(clk)
|
ws2812_inst: entity work.ws2812
|
||||||
begin
|
generic map (
|
||||||
if rising_edge(clk) then
|
NUM_LEDS => 20,
|
||||||
if count = 10000000 then
|
COLOR_ORDER => "GRB",
|
||||||
count <= 0;
|
T_CLK => 12.5 ns,
|
||||||
count2 <= count2 + 1;
|
|
||||||
else
|
|
||||||
count <= count + 1;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
drivers <= (15 downto 4 => '0') & std_logic_vector(count2);
|
T0H => 0.35 us,
|
||||||
|
T0L => 0.8 us,
|
||||||
|
T1H => 0.7 us,
|
||||||
|
T1L => 0.6 us,
|
||||||
|
|
||||||
|
T_RES => 80 us
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
n_reset => not reset,
|
||||||
|
clk => clk,
|
||||||
|
|
||||||
|
led_addr => open,
|
||||||
|
|
||||||
|
led_red => x"ff",
|
||||||
|
led_green => x"00",
|
||||||
|
led_blue => x"ff",
|
||||||
|
|
||||||
|
dout => driver_out
|
||||||
|
);
|
||||||
|
|
||||||
|
-- https://github.com/YosysHQ/yosys/issues/3360
|
||||||
|
drivers <= (19 => driver_out, others => '0');
|
||||||
end architecture;
|
end architecture;
|
||||||
|
|
Loading…
Reference in a new issue