From 57e6daedcccb59465d4956651c9b8414bcf5f21f Mon Sep 17 00:00:00 2001
From: Xiretza <xiretza@xiretza.xyz>
Date: Sun, 5 Jun 2022 16:42:26 +0200
Subject: [PATCH] vhdl: move ws2812 driver to splink module

---
 vhdl/arty_a7.vhdl | 47 +++++++----------------------------------------
 vhdl/splink.vhdl  | 47 ++++++++++++++++++++++++++++++-----------------
 2 files changed, 37 insertions(+), 57 deletions(-)

diff --git a/vhdl/arty_a7.vhdl b/vhdl/arty_a7.vhdl
index 6419831..e079fa2 100644
--- a/vhdl/arty_a7.vhdl
+++ b/vhdl/arty_a7.vhdl
@@ -16,8 +16,8 @@ entity arty_a7 is
 		-- Pmod connectors - A+D standard, B+C high-speed.
 		-- Defined as inputs by default for safety, change
 		-- when necessary
-		pmod_a : in std_logic_vector(7 downto 0);
-		pmod_b : in std_logic_vector(7 downto 0);
+		pmod_a : out std_logic_vector(7 downto 0);
+		pmod_b : out std_logic_vector(7 downto 0);
 		pmod_c : in std_logic_vector(7 downto 0);
 		pmod_d : out std_logic_vector(7 downto 0);
 
@@ -46,7 +46,7 @@ entity arty_a7 is
 end arty_a7;
 
 architecture a of arty_a7 is
-	constant NUM_DRIVERS: positive := 16;
+	constant NUM_DRIVERS: positive := 24;
 	signal drivers: std_logic_vector(NUM_DRIVERS-1 downto 0);
 
 	component liteeth_core is
@@ -180,7 +180,7 @@ architecture a of arty_a7 is
 
 	signal sys_reset : std_logic;
 begin
-	--leds_simple <= (others => '0');
+	leds_simple <= (others => '0');
 	led0 <= (others => '0');
 	led1 <= (others => '0');
 	led2 <= (others => '0');
@@ -191,8 +191,6 @@ begin
 	ck_dig_l <= (others => 'Z');
 	ck_dig_h <= (others => 'Z');
 
-	leds_simple <= drivers(3 downto 0);
-
 	liteeth_inst: liteeth_core port map (
 		sys_clock => clk_sys,
 		sys_reset => sys_reset,
@@ -284,40 +282,9 @@ begin
 
 	sys_reset <= not pll_locked or not n_reset;
 
-	ws2812_inst: entity work.ws2812
-		generic map (
-			NUM_LEDS => 20,
-			COLOR_ORDER => "GRB",
-			T_CLK => 12.5 ns,
-
-			T0H => 0.35 us,
-			T0L => 0.8 us,
-			T1H => 0.7 us,
-			T1L => 0.6 us,
-
-			T_RES => 80 us
-		)
-		port map (
-			n_reset => not sys_reset,
-			clk     => clk_sys,
-
-			led_addr => open,
-
-			led_red   => x"ff",
-			led_green => x"00",
-			led_blue  => x"ff",
-
-			dout => pmod_d(3)
-		);
-
-	-- https://github.com/YosysHQ/yosys/issues/3360
-	pmod_d(0) <= '0';
-	pmod_d(1) <= '0';
-	pmod_d(2) <= '0';
-	pmod_d(4) <= '0';
-	pmod_d(5) <= '0';
-	pmod_d(6) <= '0';
-	pmod_d(7) <= '0';
+	pmod_a <= drivers(7 downto 0);
+	pmod_b <= drivers(15 downto 8);
+	pmod_d <= drivers(23 downto 16);
 
 	sender: process(clk_sys)
 		constant COUNTER_MAX: natural := 80000000;
diff --git a/vhdl/splink.vhdl b/vhdl/splink.vhdl
index 32bf7da..cf3c8a2 100644
--- a/vhdl/splink.vhdl
+++ b/vhdl/splink.vhdl
@@ -4,9 +4,8 @@ use ieee.numeric_std.all;
 
 entity splink is
 	generic (
-		NUM_DRIVERS : positive := 16;
-		ROWS : positive := 100;
-		COLS : positive := 100
+		NUM_DRIVERS : positive;
+		MAX_STRAND_LEN : positive := 256
 	);
 	port (
 		clk : in std_logic;
@@ -17,20 +16,34 @@ entity splink is
 end entity;
 
 architecture a of splink is
-	signal count2: unsigned(3 downto 0);
-	signal count: natural range 0 to 10000000;
+	signal driver_out : std_logic;
 begin
-	process(clk)
-	begin
-		if rising_edge(clk) then
-			if count = 10000000 then
-				count <= 0;
-				count2 <= count2 + 1;
-			else
-				count <= count + 1;
-			end if;
-		end if;
-	end process;
+	ws2812_inst: entity work.ws2812
+		generic map (
+			NUM_LEDS => 20,
+			COLOR_ORDER => "GRB",
+			T_CLK => 12.5 ns,
 
-	drivers <= (15 downto 4 => '0') & std_logic_vector(count2);
+			T0H => 0.35 us,
+			T0L => 0.8 us,
+			T1H => 0.7 us,
+			T1L => 0.6 us,
+
+			T_RES => 80 us
+		)
+		port map (
+			n_reset => not reset,
+			clk     => clk,
+
+			led_addr => open,
+
+			led_red   => x"ff",
+			led_green => x"00",
+			led_blue  => x"ff",
+
+			dout => driver_out
+		);
+
+	-- https://github.com/YosysHQ/yosys/issues/3360
+	drivers <= (19 => driver_out, others => '0');
 end architecture;