Xiretza cf81fd7593 day2/vhdl: don't simulate synthesized design by default		2020-12-06 16:39:29 +01:00
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vhdl	day2/vhdl: don't simulate synthesized design by default	2020-12-06 16:39:29 +01:00
day2.py	read problem inputs from stdin	2020-12-06 16:39:29 +01:00