7 commits

Author	SHA1	Message	Date
Xiretza	cf81fd7593	day2/vhdl: don't simulate synthesized design by default	2020-12-06 16:39:29 +01:00
Xiretza	c5d334348a	read problem inputs from stdin	2020-12-06 16:39:29 +01:00
Xiretza	2e6907c604	day2/vhdl: update gitignore	2020-12-02 21:21:12 +01:00
Xiretza	354773886f	day2/vhdl: also run synthesized version	2020-12-02 21:19:33 +01:00
Xiretza	a73387e367	day2/vhdl: workaround ghdl#1529 ... https://github.com/ghdl/ghdl/pull/1529	2020-12-02 21:19:19 +01:00
Xiretza	58ae72a8aa	day2: add VHDL solution	2020-12-02 11:10:43 +01:00
Xiretza	693ed4558e	day2: add python solution	2020-12-02 08:02:49 +01:00