72 lines
1.5 KiB
VHDL
72 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all,
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ieee.numeric_std.all;
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use work.util.all;
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entity top is
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generic (
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MAX_INPUT_DIGITS : positive;
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OUTPUT_WIDTH : positive;
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STEP : natural range 1 to 2
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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char : in character;
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input_valid : in std_logic;
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output : out unsigned(OUTPUT_WIDTH-1 downto 0);
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output_valid : out std_logic
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);
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end entity;
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architecture arch of top is
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function get_window_size return positive is
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begin
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if STEP = 1 then
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return 1;
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else
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return 3;
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end if;
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end function;
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constant WINDOW_SIZE : positive := get_window_size;
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type number_t is array(MAX_INPUT_DIGITS-1 downto 0) of digit_t;
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type window_t is array(0 to WINDOW_SIZE) of number_t;
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signal window : window_t;
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signal window_countdown : natural range WINDOW_SIZE downto 0 := 0;
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if reset then
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output <= (others => '0');
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output_valid <= '1';
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window_countdown <= 0;
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elsif input_valid then
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output_valid <= '0';
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if char = LF then
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if window_countdown = WINDOW_SIZE then
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if window(0) > window(window'high) then
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output <= output + 1;
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end if;
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output_valid <= '1';
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else
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window_countdown <= window_countdown + 1;
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end if;
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window <= number_t'(others => 0) & window(0 to window'high-1);
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else
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window(0) <= window(0)(MAX_INPUT_DIGITS-2 downto 0) & char_to_digit(char);
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end if;
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end if;
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end if;
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end process;
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end architecture;
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