library ieee;
use ieee.std_logic_1164.all,
	ieee.numeric_std.all;

use work.util.all;

entity top is
	generic (
		MAX_INPUT_DIGITS : positive;
		OUTPUT_WIDTH : positive;
		STEP : natural range 1 to 2
	);
	port (
		clk : in std_logic;
		reset : in std_logic;

		char  : in character;
		input_valid : in std_logic;

		output : out unsigned(OUTPUT_WIDTH-1 downto 0);
		output_valid : out std_logic
	);
end entity;

architecture arch of top is
	function get_window_size return positive is
	begin
		if STEP = 1 then
			return 1;
		else
			return 3;
		end if;
	end function;

	constant WINDOW_SIZE : positive := get_window_size;

	type number_t is array(MAX_INPUT_DIGITS-1 downto 0) of digit_t;
	type window_t is array(0 to WINDOW_SIZE) of number_t;

	signal window : window_t;

	signal window_countdown : natural range WINDOW_SIZE downto 0 := 0;
begin
	process(clk)
	begin
		if rising_edge(clk) then
			if reset then
				output <= (others => '0');
				output_valid <= '1';
				window_countdown <= 0;
			elsif input_valid then
				output_valid <= '0';

				if char = LF then
					if window_countdown = WINDOW_SIZE then
						if window(0) > window(window'high) then
							output <= output + 1;
						end if;
						output_valid <= '1';
					else
						window_countdown <= window_countdown + 1;
					end if;

					window <= number_t'(others => 0) & window(0 to window'high-1);
				else
					window(0) <= window(0)(MAX_INPUT_DIGITS-2 downto 0) & char_to_digit(char);
				end if;
			end if;
		end if;
	end process;
end architecture;