84 lines
1.8 KiB
VHDL
84 lines
1.8 KiB
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all,
|
|
ieee.numeric_std.all;
|
|
|
|
entity top is
|
|
generic (
|
|
COUNTER_WIDTH : positive;
|
|
STEP : natural range 1 to 2
|
|
);
|
|
port (
|
|
clk : in std_logic;
|
|
reset : in std_logic;
|
|
char : in character;
|
|
is_record : in std_logic;
|
|
num_verified : out unsigned(COUNTER_WIDTH-1 downto 0)
|
|
);
|
|
end entity;
|
|
|
|
architecture behaviour of top is
|
|
signal is_data : std_logic;
|
|
signal num1, num2 : natural range 0 to 99;
|
|
signal letter : character;
|
|
|
|
signal prev_is_record : std_logic;
|
|
signal record_ended : std_logic;
|
|
|
|
signal verified : std_logic;
|
|
begin
|
|
record_ended <= prev_is_record and not is_record;
|
|
|
|
parser_inst: entity work.parser
|
|
port map (
|
|
clk => clk,
|
|
reset => reset,
|
|
is_record => is_record,
|
|
is_data => is_data,
|
|
char => char,
|
|
|
|
num1 => num1,
|
|
num2 => num2,
|
|
letter => letter
|
|
);
|
|
|
|
generate_verifier: if step = 1 generate
|
|
verifier_inst: entity work.verifier(step1)
|
|
port map (
|
|
clk => clk,
|
|
reset => reset or record_ended,
|
|
is_data => is_data,
|
|
num1 => num1,
|
|
num2 => num2,
|
|
letter => letter,
|
|
char => char,
|
|
verified => verified
|
|
);
|
|
elsif step = 2 generate
|
|
verifier_inst: entity work.verifier(step2)
|
|
port map (
|
|
clk => clk,
|
|
reset => reset or record_ended,
|
|
is_data => is_data,
|
|
num1 => num1,
|
|
num2 => num2,
|
|
letter => letter,
|
|
char => char,
|
|
verified => verified
|
|
);
|
|
else generate
|
|
assert false report "Bad value for ""step""" severity failure;
|
|
end generate;
|
|
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
prev_is_record <= is_record;
|
|
if reset then
|
|
prev_is_record <= '0';
|
|
num_verified <= (others => '0');
|
|
elsif record_ended and verified then
|
|
num_verified <= num_verified + 1;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
end architecture;
|