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3ab9f6bb2e
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2020 day2/vhdl: don't simulate synthesized design by default
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2021-12-01 08:54:50 +01:00 |
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753a0e7034
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read problem inputs from stdin
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2021-12-01 08:54:50 +01:00 |
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7201d8c28a
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2020 day2/vhdl: also run synthesized version
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2021-12-01 08:54:50 +01:00 |
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791b6f62aa
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2020 day2/VHDL: add solution
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2021-12-01 08:54:50 +01:00 |
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