76 lines
2.7 KiB
TeX
76 lines
2.7 KiB
TeX
\subsection{Parallel bus}
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The core part of the hardware is the interface between the microprocessor and
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the hardware peripherials. This bus is delivering data in parallel and is
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therefore named the ``parallel bus``. This bus has 3 different sub-parts:
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\begin{enumerate}
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\item{The address bus}
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\item{The data bus}
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\item{The control bus}
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\end{enumerate}
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This split is common in many computer architectures and bus systems used by
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various microprocessor manufacturers. In figure \ref{fig:atari_pbi} the
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layout of the Atari Parallel Bus Interface is shown as used on the Atari 800XL.
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\begin{figure}[H]
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\includegraphics[width=\textwidth, angle=0]{pics/atari_pbi}
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\caption{Atari PBI Pinout;Source: \url{https://www.atarimagazines.com}}
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\label{fig:atari_pbi}
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\end{figure}
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\subsubsection{Address Bus}
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The address bus contains the nescessary data lines for addressing the individual
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registers of the Serial connection and the uart. On any modern system this bus
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is from 16 to 64 bits wide. For our implementation the bus size was chosen to
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be 8 bit, which is multiple times the amount of needed address space, but
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is the smallest addressable unit on most microcontroller architectures and
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therefore easy to program with. The address bus is unidirectional.
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\subsection{Data Bus}
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The data bus contains the actual data to be stored to and read from registers.
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The data bus is, as well on most systems a multiple of 16 bits wide, but for the
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same reasons as the data bus, was shrunk down in our case to 8 bits. The data
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bus is bidirectional.
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\subsection{Control Bus}
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Control bus is a term which referes to any control lines (such as read and write
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lines or clock lines) which are neither address nor data bus. The control bus
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in our case needed to be 5 bits wide and consists of:
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\begin{itemize}
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\item{$MR$ ... Master Reset}
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\item{$\lnot WR$ ... Write Not}
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\item{$\lnot RD$ ... Read Not}
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\item{$\lnot MS1$ ... Module Select 1 Not}
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\item{$\lnot MS2$ ... Module Select 2 Not}
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\end{itemize}
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\subsubsection{Master Reset}
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A high level on the $MR$ lane signals to the peripherials that a reset of all
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registers and states should occure. This is needed for the serial console and
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the dac.
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\subsubsection{Write Not}
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A low level on the $\lnot WR$ lane signals the corresponding modules that the
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data on
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the data bus should be written to the register on the address specified from the
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address bus.
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\subsubsection{Read Not}
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A low level on the $\lnot RD$ lane signals the corresponding modules that the
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data
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from the register specified by the address on the address bus should be written
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to the data bus.
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\subsubsection{Module Select 1 and 2 Not}
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A low level on one of these lines signals the corresponding module that the
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data on address data and the control lines is meant for it.
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