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tyrolyean
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dipl
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bf239165f8
dipl
/
vhdl_intro
/
vhdl
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Xiretza
279e78331b
Update Hello World example, demonstrate synthesis
2020-03-20 10:16:40 +01:00
..
.gitignore
Update Hello World example, demonstrate synthesis
2020-03-20 10:16:40 +01:00
counter.vhd
Update Hello World example, demonstrate synthesis
2020-03-20 10:16:40 +01:00
counter.xdc
Update Hello World example, demonstrate synthesis
2020-03-20 10:16:40 +01:00
counter_tb.gtkw
Update Hello World example, demonstrate synthesis
2020-03-20 10:16:40 +01:00
counter_tb.vhd
Update Hello World example, demonstrate synthesis
2020-03-20 10:16:40 +01:00