dipl/sections/core/entities/exception_control_entity.vhd

36 lines
No EOL
956 B
VHDL

entity exception_control is
port (
clk : in std_logic;
fetch_raise_exc : in std_logic;
fetch_exc_data : in exception_data_t;
-- synchronous exceptions
decoder_raise_exc : in std_logic;
decoder_exc_data : in exception_data_t;
csr_raise_exc : in std_logic;
csr_exc_data : in exception_data_t;
alignment_raise_exc : in std_logic;
alignment_exc_data : in exception_data_t;
datamem_raise_exc : in std_logic;
datamem_exc_data : in exception_data_t;
-- interrupts
global_int_enabled : in std_logic;
interrupts_enabled : in yarm_word;
interrupts_pending : in yarm_word;
-- stage inputs for return address + trap value (instruction)
stage_inputs : in pipeline_frames_t;
interrupted_stage : in pipeline_stage_t;
may_interrupt : in std_logic;
do_trap : out std_logic;
trap_cause : out yarm_trap_cause;
trap_address : out yarm_word;
trap_value : out yarm_word
);
end exception_control;