31 lines
899 B
VHDL
31 lines
899 B
VHDL
entity memory_arbiter is
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port (
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clk : in std_logic;
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reset : in std_logic;
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fetch_enable : in std_logic;
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fetch_ready : out std_logic;
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fetch_address : in yarm_word;
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fetch_instr_out : out yarm_word;
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fetch_raise_exc : out std_logic;
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fetch_exc_data : out exception_data_t;
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datamem_enable : in std_logic;
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datamem_ready : out std_logic;
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datamem_instr_info_in : in instruction_info_t;
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datamem_read_data : out yarm_word;
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datamem_raise_exc : out std_logic;
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datamem_exc_data : out exception_data_t;
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-- little-endian memory interface, 4 byte address alignment
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MEM_addr : out yarm_word;
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MEM_read : out std_logic;
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MEM_write : out std_logic;
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MEM_ready : in std_logic;
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MEM_byte_enable : out std_logic_vector(3 downto 0);
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MEM_data_read : in yarm_word;
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MEM_data_write : out yarm_word
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);
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end memory_arbiter; |