718 lines
26 KiB
Plaintext
718 lines
26 KiB
Plaintext
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\endverb
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{{hash=88f8ec899081963e23b83d8acba08c65}{%
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family={Contributors},
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\verb https://github.com/YosysHQ/yosys
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\endverb
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\verb{url}
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\verb{url}
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\verb https://github.com/tgingold/ghdlsynth-beta
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\entry{nextpnr-xilinx}{software}{}
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{{hash=b63d41e5c93c4d17378cba0a2c92ead5}{%
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family={Shah},
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\entry{prjxray}{online}{}
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{{hash=b708aa1a1e59b231108bb03e4e723ebe}{%
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\entry{open-fpga-loader}{software}{}
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{{hash=1bd2a62be5780bc03aa7495001f435f8}{%
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family={Goavec-Merou},
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\entry{nandgame}{online}{}
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{{hash=4a90198698fb32d663d36c51edb69843}{%
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family={Kjær},
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given={Olav\bibnamedelima Junker},
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\entry{breadboard_computer}{online}{}
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\name{author}{1}{}{%
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{{hash=b0474bcb5b920e72f686bbce7845cc62}{%
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\entry{yosys-paper}{unpublished}{}
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\name{author}{1}{}{%
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{{hash=5991168ed2757d832c421dbfb7b4dd74}{%
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family={Clifford\bibnamedelima Wolf},
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giveni={J\bibinitperiod\bibinitdelim G\bibinitperiod}}}%
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\field{title}{Yosys - A Free Verilog Synthesis Suite}
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|
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|
\verb{urlraw}
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|
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|
\verb http://www.clifford.at/yosys/files/yosys-austrochip2013.pdf
|
|
\endverb
|
|
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|
|
\entry{nextpnr}{software}{}
|
|
\name{author}{1}{}{%
|
|
{{hash=88f8ec899081963e23b83d8acba08c65}{%
|
|
family={Contributors},
|
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familyi={C\bibinitperiod},
|
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given={Various},
|
|
giveni={V\bibinitperiod}}}%
|
|
}
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\verb{url}
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|
\entry{liteeth}{software}{}
|
|
\name{author}{1}{}{%
|
|
{{hash=e9c489119ad4942770b6bd4290d69375}{%
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family={Kermarrec},
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given={Florent},
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\entry{riscv-compliance}{online}{}
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\name{author}{1}{}{%
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{{hash=e4142e71f6cef3500ab2f7f718c34c72}{%
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family={Jeremy\bibnamedelima Bennett},
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giveni={L\bibinitperiod\bibinitdelim M\bibinitperiod}}}%
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|
\endrefsection
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|
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|