dipl/vhdl_intro/vhdl
2020-03-20 10:16:40 +01:00
..
.gitignore Update Hello World example, demonstrate synthesis 2020-03-20 10:16:40 +01:00
counter.vhd Update Hello World example, demonstrate synthesis 2020-03-20 10:16:40 +01:00
counter.xdc Update Hello World example, demonstrate synthesis 2020-03-20 10:16:40 +01:00
counter_tb.gtkw Update Hello World example, demonstrate synthesis 2020-03-20 10:16:40 +01:00
counter_tb.vhd Update Hello World example, demonstrate synthesis 2020-03-20 10:16:40 +01:00