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Author SHA1 Message Date
Tyrolyean
af6338dbd3
Sanitized bibliography 
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
 2020-03-27 13:00:18 +01:00
Tyrolyean
d1e846960c
Merge remote-tracking branch 'iteasyndikat/batman-release-20200327' into waschtl 
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
 2020-03-27 12:58:29 +01:00
Xiretza
8492d24c27
Release batman-2020-03-27 2020-03-27 12:52:42 +01:00
Xiretza
ad723217ad
Add information about external bus 2020-03-27 12:50:24 +01:00
Xiretza
244380ee5f
Fix citations, change citation style 2020-03-27 12:49:50 +01:00
Xiretza
e65030ef47
Add information about riscv compliance tests 2020-03-27 12:49:38 +01:00
25 changed files with 1798 additions and 1279 deletions
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Diplomschrift.pdf Normal file
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2
Makefile
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@ -27,7 +27,7 @@ entity_headers: $(HEADER_DIRS)
.PHONY: Diplomschrift.pdf .PHONY: Diplomschrift.pdf
Diplomschrift.pdf: $(HEADER_DIRS) Diplomschrift.tex Diplomschrift.pdf: $(HEADER_DIRS) Diplomschrift.tex
latexmk --pdfxe --pdfxelatex="xelatex -interaction=nonstopmode --shell-escape" --use-make Diplomschrift.tex latexmk --pdfxe --pdfxelatex="lualatex -interaction=nonstopmode --shell-escape" --use-make Diplomschrift.tex
.PHONY: clean .PHONY: clean
clean: clean:

6
Diplomschrift.bib → bibliographies/AB.bib
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@ -71,3 +71,9 @@
title = {GTKWave}, title = {GTKWave},
url = {http://gtkwave.sourceforge.net}, url = {http://gtkwave.sourceforge.net},
} }
@online{riscv-compliance,
author = {Jeremy Bennett, Lee Moore},
title = {RISC-V Compliance Task Group},
url = {https://github.com/riscv/riscv-compliance},
}

374
main.aux
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main.tex
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@ -138,11 +138,10 @@ interpreted as gender neutral.
\DP\input{sections/DP/fpga_interface/main.tex} \DP\input{sections/DP/fpga_interface/main.tex}
\DP\input{sections/DP/textadv/main.tex} \DP\input{sections/DP/textadv/main.tex}
\clearpage \clearpage
%\MR\input{sections/Kapitel/MR/EntwicklungAufgaben.tex}
\subfile{sections/vhdl_intro/vhdl_intro.tex} \AB\subfile{sections/vhdl_intro/vhdl_intro.tex}
\subfile{sections/soc/soc.tex} \AB\subfile{sections/soc/soc.tex}
\subfile{sections/core/core.tex} \AB\subfile{sections/core/core.tex}
%==================================================================================== %====================================================================================
\allAuth \allAuth

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main.toc
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@ -1,69 +0,0 @@
\babel@toc {english}{}
\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax
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\contentsline {section}{Gendererklärung}{i}{Doc-Start}%
\contentsline {section}{Kurzfassung/Abstract}{ii}{Doc-Start}%
\babel@toc {ngerman}{}
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\contentsline {section}{Result}{iii}{Doc-Start}%
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\contentsline {section}{\numberline {1}Task description}{1}{section.1}%
\contentsline {subsection}{\numberline {1.1}Hardware}{1}{subsection.1.1}%
\contentsline {section}{\numberline {2}Hardware peripherials}{2}{section.2}%
\contentsline {subsection}{\numberline {2.1}Parallel bus}{2}{subsection.2.1}%
\contentsline {subsubsection}{\numberline {2.1.1}Address Bus}{2}{subsubsection.2.1.1}%
\contentsline {subsection}{\numberline {2.2}Data Bus}{3}{subsection.2.2}%
\contentsline {subsection}{\numberline {2.3}Control Bus}{3}{subsection.2.3}%
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\contentsline {subsubsection}{\numberline {2.8.4}Schematics}{20}{subsubsection.2.8.4}%
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\contentsline {paragraph}{NE55 Clock Source}{22}{figure.caption.17}%
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\contentsline {paragraph}{SAW Generator}{23}{subsubsection.2.8.5}%
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\contentsline {section}{\numberline {3}Addressing DACA and DACB}{26}{section.3}%
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3
preamble.tex
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@ -149,9 +149,10 @@
\makeindex \makeindex
%%% BibLaTeX settings %%% BibLaTeX settings
\usepackage[citestyle = ieee]{biblatex} \usepackage[style = verbose, dashed=false, citestyle = ieee]{biblatex}
\usepackage{csquotes} \usepackage{csquotes}
\addbibresource{./bibliographies/DP.bib} \addbibresource{./bibliographies/DP.bib}
\addbibresource{./bibliographies/AB.bib}
\DeclareNameAlias{sortname}{family-given} \DeclareNameAlias{sortname}{family-given}
\renewcommand\multinamedelim{;\ } \renewcommand\multinamedelim{;\ }
\renewcommand\finalnamedelim{;\ } \renewcommand\finalnamedelim{;\ }

2
sections/DP/textadv/main.tex
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@ -13,7 +13,7 @@ Like the before examples, the textadventure was implemented on an ATMega2560
and uses 3 different Registers for transmission: PORTF, PORTK and PORTL for and uses 3 different Registers for transmission: PORTF, PORTK and PORTL for
address bus, data bus and control bus respectively, as can be seen in listing address bus, data bus and control bus respectively, as can be seen in listing
\ref{lst:textadv-avr.h} \ref{lst:textadv-avr.h}
\newpage
\lstinputlisting[language=C,frame=trBL, \lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage, breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-avr.h}, caption={The avr.h header file}, label={lst:textadv-avr.h}, caption={The avr.h header file},

18
sections/core/entities/alu_entity.vhd Normal file
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@ -0,0 +1,18 @@
entity alu is
port (
clk : in std_logic;
enable_math : in std_logic;
valid : out std_logic;
operation : in alu_operation_t;
a, b : in yarm_word;
math_result : out yarm_word;
-- compare inputs
-- do signed comparisons
enable_cmp : in std_logic;
cmp_signed : in std_logic;
cmp1, cmp2 : in yarm_word;
cmp_result : out compare_result_t
);
end alu;

54
sections/core/entities/control_entity.vhd Normal file
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@ -0,0 +1,54 @@
entity control is
generic (
RESET_VECTOR : yarm_word
);
port (
clk : in std_logic;
reset : in std_logic;
fetch_enable : out std_logic;
fetch_ready : in std_logic;
fetch_instr_out : in yarm_word;
decoder_enable : out std_logic;
decoder_instr_info_out : in instruction_info_t;
registers_data_a : in yarm_word;
registers_data_b : in yarm_word;
alu_enable_math : out std_logic;
alu_math_result : in yarm_word;
alu_valid : in std_logic;
alu_enable_cmp : out std_logic;
alu_cmp_result : in compare_result_t;
csr_enable : out std_logic;
csr_ready : in std_logic;
csr_data_read : in yarm_word;
csr_increase_instret : out std_logic;
datamem_enable : out std_logic;
datamem_ready : in std_logic;
alignment_raise_exc : out std_logic;
alignment_exc_data : out exception_data_t;
registers_read_enable : out std_logic;
registers_write_enable : out std_logic;
-- TRAP CONTROL
may_interrupt : out std_logic;
-- the stage that will receive an interrupt exception
interrupted_stage : out pipeline_stage_t;
do_trap : in std_logic;
trap_vector : in yarm_word;
trap_return_vec : in yarm_word;
return_trap : out std_logic;
-- instruction info records used as input for the respective stages
stage_inputs : out pipeline_frames_t
);
end control;

23
sections/core/entities/core_entity.vhd Normal file
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@ -0,0 +1,23 @@
entity core is
generic (
HART_ID : natural;
RESET_VECTOR : yarm_word := (others => '0')
);
port (
clk : in std_logic;
reset : in std_logic;
-- little-endian memory interface, 4 byte address alignment
MEM_addr : out yarm_word;
MEM_read : out std_logic;
MEM_write : out std_logic;
MEM_ready : in std_logic;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word;
external_int : in std_logic;
timer_int : in std_logic;
software_int : in std_logic
);
end core;

36
sections/core/entities/csr_entity.vhd Normal file
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@ -0,0 +1,36 @@
entity csr is
generic (
HART_ID : integer
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
ready : out std_logic;
instr_info_in : in instruction_info_t;
data_write : in yarm_word;
data_read : out yarm_word;
increase_instret : in std_logic;
external_int : in std_logic;
timer_int : in std_logic;
software_int : in std_logic;
interrupts_pending : out yarm_word;
interrupts_enabled : out yarm_word;
global_int_enabled : out std_logic;
mtvec_out : out yarm_word;
mepc_out : out yarm_word;
do_trap : in std_logic;
return_m_trap : in std_logic;
mepc_in : in yarm_word;
mcause_in : in yarm_trap_cause;
mtval_in : in yarm_word;
raise_exc : out std_logic;
exc_data : out exception_data_t
);
end csr;

21
sections/core/entities/decoder_entity.vhd Normal file
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@ -0,0 +1,21 @@
entity decoder is
port (
clk : in std_logic;
enable : in std_logic;
async_addr_rs1 : out register_addr_t;
async_addr_rs2 : out register_addr_t;
alu_muxsel_a : out mux_selector_t;
alu_muxsel_b : out mux_selector_t;
alu_muxsel_cmp2 : out mux_selector_t;
csr_muxsel_in : out mux_selector_t;
instr_info_in : in instruction_info_t;
instr_info_out : out instruction_info_t;
raise_exc : out std_logic;
exc_data : out exception_data_t
);
end decoder;

36
sections/core/entities/exception_control_entity.vhd Normal file
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@ -0,0 +1,36 @@
entity exception_control is
port (
clk : in std_logic;
fetch_raise_exc : in std_logic;
fetch_exc_data : in exception_data_t;
-- synchronous exceptions
decoder_raise_exc : in std_logic;
decoder_exc_data : in exception_data_t;
csr_raise_exc : in std_logic;
csr_exc_data : in exception_data_t;
alignment_raise_exc : in std_logic;
alignment_exc_data : in exception_data_t;
datamem_raise_exc : in std_logic;
datamem_exc_data : in exception_data_t;
-- interrupts
global_int_enabled : in std_logic;
interrupts_enabled : in yarm_word;
interrupts_pending : in yarm_word;
-- stage inputs for return address + trap value (instruction)
stage_inputs : in pipeline_frames_t;
interrupted_stage : in pipeline_stage_t;
may_interrupt : in std_logic;
do_trap : out std_logic;
trap_cause : out yarm_trap_cause;
trap_address : out yarm_word;
trap_value : out yarm_word
);
end exception_control;

16
sections/core/entities/memctl_entity.vhd Normal file
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@ -0,0 +1,16 @@
entity memctl is
port (
addr : in yarm_word;
-- data width
data_width : in datum_width_t;
-- perfom sign extension when reading short data
sign_extend : in std_logic;
data_read : out yarm_word;
data_write : in yarm_word;
MEM_addr : out yarm_word;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word
);
end memctl;

31
sections/core/entities/memory_arbiter_entity.vhd Normal file
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@ -0,0 +1,31 @@
entity memory_arbiter is
port (
clk : in std_logic;
reset : in std_logic;
fetch_enable : in std_logic;
fetch_ready : out std_logic;
fetch_address : in yarm_word;
fetch_instr_out : out yarm_word;
fetch_raise_exc : out std_logic;
fetch_exc_data : out exception_data_t;
datamem_enable : in std_logic;
datamem_ready : out std_logic;
datamem_instr_info_in : in instruction_info_t;
datamem_read_data : out yarm_word;
datamem_raise_exc : out std_logic;
datamem_exc_data : out exception_data_t;
-- little-endian memory interface, 4 byte address alignment
MEM_addr : out yarm_word;
MEM_read : out std_logic;
MEM_write : out std_logic;
MEM_ready : in std_logic;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word
);
end memory_arbiter;

20
sections/core/entities/multiplier_entity.vhd Normal file
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@ -0,0 +1,20 @@
entity multiplier is
generic (
-- A shorter than B: faster, but wider adder required
WIDTH_A : positive;
WIDTH_B : positive
--PARALLELISM : positive
);
port (
clk : in std_logic;
run : in std_logic;
valid : out std_logic;
mul_signed : in std_logic;
a : in std_logic_vector(WIDTH_A-1 downto 0);
b : in std_logic_vector(WIDTH_B-1 downto 0);
result : out std_logic_vector(WIDTH_A+WIDTH_B-1 downto 0)
);
end multiplier;

9
sections/core/entities/program_counter_entity.vhd Normal file
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@ -0,0 +1,9 @@
entity program_counter is
port (
clk : in std_logic;
reset : in std_logic;
operation : in pc_operation_t;
pc_in : in yarm_word;
pc_out : out yarm_word
);
end program_counter;

16
sections/core/entities/registers_entity.vhd Normal file
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@ -0,0 +1,16 @@
entity registers is
port (
clk : in std_logic;
read_enable : in std_logic;
write_enable : in std_logic;
addr_a : in register_addr_t;
addr_b : in register_addr_t;
addr_d : in register_addr_t;
data_a : out yarm_word;
data_b : out yarm_word;
data_d : in yarm_word
);
end registers;

22
sections/soc/soc.tex
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@ -143,4 +143,26 @@ The exact timing differs between models, so all periods can be customized using
% TODO % TODO
\subsection{External Bus}
Bridging the internal SoC bus with the external peripheral bus requires a few steps. For one, the external data bus is bidirectional, so tri-state outputs must be used on the FPGA. In addition, the internal bus arbitrates components using addresses alone, while the external bus uses chip enable signals and overlapping address spaces.
Due to a mistake in the adapter board layout, the nibbles of the address and data buses are reversed (MSB to LSB are pins 7 to 0 on the FPGA, but 3 to 0 followed by 7 to 4 on the board). Thanks to the completely arbitrary mapping of FPGA pins, this can be mitigated without using any additional resources.
\section{Testing}
\subsection{RISC-V Compliance Tests}
The RISC-V Compliance Test Suite\cite{riscv-compliance} can be used to empirically confirm the correct functionality of a RISC-V processor. It consists of a series of programs that perform some operations related to a specific feature, then write some result data to a memory region. This memory region is then compared to a ``golden signature'', which was produced by a processor implementation that is known to be correct.
The initial implementation of the compliance tests uncovered several bugs in the processor core:
\begin{itemize}
\item The bitshift instructions (SLL, SRL, SRA, etc.) must, according to the RISC-V standard, only use the lower 5 bits of the second operand as a shift offset. The implementation used all 31 bits instead, causing a test failure.
\item Reading a signed value of a size less than 32 bits from memory would not perform proper sign extension. For example, reading a byte value of 0xFF (-1) would result in an expanded machine word of 0x0000_00FF (255) instead of 0xFFFF_FFFF.
\item The \icode{SLTIU} (Set less than immediate; unsigned) instruction compares a given register with a constant provided as part of the instruction (the immediate). While the comparison is unsigned, the 12-bit immediate must be sign-extended as if it were a signed integer. The implementation wrongly assumed that the sign-extension should be unsigned as well.
\item The Instruction Set Manual specifies exceptions that must be raised when a misaligned memory access occurs. These exceptions were not yet implemented, but since the compliance tests check for them, the functionality was added to make the tests pass.
\end{itemize}
Since these tests are easily automated, they were added to the GitLab Continuous Integration (CI) configuration. Whenever a new git commit is pushed to GitLab, the tests are run automatically, and any failures are reported to the responsible committer via email.
\end{document} \end{document}

2
sections/vhdl_intro/vhdl_intro.tex
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@ -14,7 +14,7 @@ Other than a text editor, the following Free Software packages have to be instal
\item[\icode{ghdl}\cite{ghdl}] to analyze, compile, and simulate the design \item[\icode{ghdl}\cite{ghdl}] to analyze, compile, and simulate the design
\item[\icode{gtkwave}\cite{gtkwave}] to view the simulation waveform files \item[\icode{gtkwave}\cite{gtkwave}] to view the simulation waveform files
\item[\icode{yosys}\cite{yosys}] to synthesize the design \item[\icode{yosys}\cite{yosys}] to synthesize the design
\item[\icode{ghdlsynth-beta}\cite{yosys}] to synthesize the design \item[\icode{ghdlsynth-beta}\cite{ghdlsynth-beta}] to synthesize the design
\item[\icode{nextpnr-xilinx}\cite{nextpnr-xilinx}] to place and route the design \item[\icode{nextpnr-xilinx}\cite{nextpnr-xilinx}] to place and route the design
\item[\icode{Project X-Ray}\cite{prjxray}] for FPGA layout data and bitstream tools \item[\icode{Project X-Ray}\cite{prjxray}] for FPGA layout data and bitstream tools
\item[\icode{openFPGALoader}\cite{open-fpga-loader}] to load the bitstream onto the FPGA \item[\icode{openFPGALoader}\cite{open-fpga-loader}] to load the bitstream onto the FPGA