Merge branch 'waschtl' into merge-all

Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>

.gitignore

@@ -17,6 +17,8 @@
 *.dvi
 *.xdv
 *.out
+*.auxlock
+*.md5
 *.kate-swp
 
 *.pdf_tex

Makefile

@@ -7,7 +7,7 @@ VHDL_DIR = $(YARM_DIRECTORY)/vhdl
 CODEDIR = code
 
 .PHONY: all
-all: Diplomschrift.pdf
+all: main.pdf
 
 $(CODEDIR):
 	mkdir -p $@
@@ -25,9 +25,9 @@ $(eval $(call headers_template,sections/core/entities/,$(wildcard $(VHDL_DIR)/co
 .PHONY: entity_headers
 entity_headers: $(HEADER_DIRS)
 
-.PHONY: Diplomschrift.pdf
-Diplomschrift.pdf: $(HEADER_DIRS) Diplomschrift.tex
-	latexmk --pdfxe --pdfxelatex="lualatex -interaction=nonstopmode --shell-escape" --use-make Diplomschrift.tex
+.PHONY: main.pdf
+main.pdf: $(HEADER_DIRS) main.tex
+	latexmk --pdflua --pdflualatex="lualatex -interaction=nonstopmode --shell-escape" --use-make main.tex
 
 .PHONY: clean
 clean:

bibliographies/AB.bib

@@ -1,3 +1,10 @@
+@online{fsf-definition,
+	author  = {Free Software Foundation},
+	title   = {What is free software?},
+	url     = {https://www.fsf.org/about/what-is-free-software},
+	urldate = {2020-03-31},
+}
+
 @online{nandgame,
     author = {Olav Junker Kjær},
     title  = {The Nand Game},

bibliographies/DP.bib

@@ -67,7 +67,7 @@
 @Manual{ad2,
 	month = Sep,
 	year = {2015},
-	title = {Analog Discovery 2™ Reference Manual},
+	title = {Analog Discovery 2\texttrademark{} Reference Manual},
 	organization = {Digilent, Inc.},
 	url = {https://reference.digilentinc.com/_media/reference/instrumentation/analog-discovery-2/ad2_rm.pdf}
 }
@@ -178,7 +178,7 @@
 
 @Manual{ac97,
 	year = {1996},
-	title = {Overview ofAudio Codec ‘97},
+	title = {Overview of Audio Codec '97},
 	organization = {Intel Corporation},
 	author = {Dan Cox},
 	url = {http://euc.jp/periphs/AC97_OVR.PDF}

main.auxlock

@@ -1 +0,0 @@
-\def \tikzexternallocked {0}

main.tex

@@ -2,11 +2,7 @@
 
 \usepackage{subfiles}
 \begin{document}
-\selectlanguage{ngerman}
 % Correct numeral usage in footnotes, figures and listings
-\renewcommand{\thefootnote}{\Alph{footnote}}
-\renewcommand{\thelstlisting}{\Roman{lstlisting}}
-\renewcommand{\thefigure}{\roman{figure}}
 
 	%/*Header-Einstellung*/
 \pagestyle{fancy}
@@ -136,15 +132,15 @@ geschlechtsunabh"angig verstanden werden soll.
 \DP\input{sections/DP/textadv/main.tex}
 \clearpage
 
-\part{FPGA-based System on Chip (SoC)}
-\AB\subfile{sections/soc/soc.tex}
+\AB\subfile{sections/fpga-development.tex}
 \AB\subfile{sections/core/core.tex}
+\AB\subfile{sections/soc/soc.tex}
 
 %====================================================================================
 \allAuth
-\selectlanguage{ngerman}
 \clearpage\vfill\newpage{}
 %====================================================================================
+\begin{otherlanguage}{ngerman}
 \section{Erkl"arung der Eigenst"andigkeit der Arbeit}
 	\noindent\\[0mm] EIDESSTATTLICHE ERKLÄRUNG
 	\\[4mm]
@@ -171,38 +167,24 @@ geschlechtsunabh"angig verstanden werden soll.
 		\rule{70mm}{.5pt}\\
 		\hspace*{3mm} Daniel Plank
 	}
-
+\end{otherlanguage}
 %====================================================================================
 \clearpage\vfill\newpage{}
-\pagenumbering{Roman}
 %====================================================================================
-\selectlanguage{english}
-\renewcommand{\thesection}{\Roman{section}\;}
-\setcounter{section}{0}
 \listoffigures\thispagestyle{fancy}
 \listoftables\thispagestyle{fancy}
 \lstlistoflistings\thispagestyle{fancy}
-\printbibliography[title={Literaturverzeichnis}]
+\printbibliography
 
 %====================================================================================
 \clearpage\vfill\newpage{}
 %====================================================================================
-\noindent\\[-2mm]
-\hspace*{3mm}{\sc\textbf{\Large Anhang}}
-\noindent\\[-5mm]
 %
 %
-\cfoot{Anhang}
-\addcontentsline{toc}{section}{Anhang}
-\appendix
-\renewcommand{\thesection}{\Alph{section}}
-\setcounter{section}{1}
-\setcounter{subsection}{0}
 
-%\subsection{Pflichtenheft}
-%\input{sections/Anhang/Pflichtenheft/pflichtenheftMR.tex}
-%
-%\newpage
+\begin{appendices}
+\cfoot{Appendices}
+\section{Projektmanagement}
 \subsection{Schlussfolgerung / Projekterfahrung}
 \input{sections/Anhang/schlussfolgerung.tex}
 \subsection{Projektplanung}
@@ -214,6 +196,7 @@ geschlechtsunabh"angig verstanden werden soll.
 %\MR\input{sections/Anhang/Arbeitsnachweis/arbeitsnachweisMR.tex}
 
 \AB\subfile{sections/vhdl_intro/vhdl_intro.tex}
+\end{appendices}
 
 \clearpage
 \label{LastPage}

preamble.tex

@@ -286,7 +286,7 @@ minimum height=1cm, align=center, text width=3cm, draw=black, fill=blue!30]
 \newcommand\TikZ{Ti\textit{k}Z}
 
 \usepackage{booktabs}
-\usepackage[toc,page]{appendix}
+\usepackage[title,toc,titletoc,page]{appendix}
 
 \newcommand{\HtlHeader}[0]{%
 	%\hspace*{-11mm}%

sections/Anhang/Projektterminplanung/projektterminplanungDP.tex

@@ -103,11 +103,11 @@ Table \ref{tab:plank_work} shows the times worked.
 	\hline
 	2020-01-26	& 6.25	& Attempting interaction with 16550 no output\\
 	\hline
-	2020-02-01	& 3	& Attempting interaction with 16550 quartz doesn’t oscillate\\
+	2020-02-01	& 3	& Attempting interaction with 16550 quartz doesn't oscillate\\
 	\hline
 	2020-02-07	& 5.5	& Attempting to make 1.8432MHz oscillators oscillate\\
 	\hline
-	2020-02-08	& 3	& Oscillation succeeded… finaly\\
+	2020-02-08	& 3	& Oscillation succeeded\dots{} finaly\\
 	\hline
 	2020-02-09	& 7.75	& Transmit character in serial via 16550\\
 	\hline

sections/DP/UART/main.tex

@@ -123,8 +123,9 @@ MAX-232 as the C1 has to the 16550-UART.
 \subsubsection{Demonstration Software}
 
 To demonstrate the functionality and prove that the schematic has no underlying
-error, a program which regularly transmits a character was written as well as
-a simple echo program, which transmits all received characters. Both programs
+error, a program which regularly transmits a character as well as
+a simple echo program, which transmits all received characters are used. 
+Both programs
 transmit 8 bit characters without parity at 38400 Baud. The output for program
 one can be seen in Figure \ref{fig:uart232} and the output for program two in
 Figure \ref{fig:232_echo}. 
@@ -150,7 +151,7 @@ Figure \ref{fig:232_echo}.
 
 \paragraph{Transmit code}
 The transmit code regularly transmits the letter capital A  via the 16550 UART.
-Before it can do this it needs to perform some initialisations. The
+Some initialisation is required beforehand. The
 functions shown in Listing \ref{lst:16550-general} are the read and write
 routines for accessing the 16550 UART. These routines also apply to the echo
 code. 
@@ -189,8 +190,8 @@ SOUT lane of the 16550 UART can be seen in Figure \ref{fig:16550A}
 The echo code permanently polls the 16550 UART wether a character has been
 received, and if yes, reads it from the receiver holding register and writes it
 back to the tx holding register. The output of this code can be seen in Figure
-\ref{fig:232_echo}. The initialisation is practically the same as for the
-transmission code, as well as the read and write routines in Listing 
+\ref{fig:232_echo}. The initialisation is practically the same for the
+echo code as well as the read and write routines in Listing
 \ref{lst:16550-general}.
 
 \lstinputlisting[language=C,frame=trBL,

sections/DP/dac/main.tex

@@ -1,7 +1,7 @@
 \subsection{Audio Digital-Analog-Converter}
 
 A digital to analog converter takes a digital number and converts it to a
-analog signal. The output of one such conversion is called a sample. With
+analog signal. The output of such a conversion is called a sample. With
 enough samples per second various different waveforms can be produced, which,
 when amplified and put onto a speaker, can be heared by the human ear as a tone.
 With various tones in series a melody can be produced, which is what the DAC in
@@ -10,15 +10,16 @@ this implementation does.
 \subsubsection{TLC 7528 Dual R2R Ladder DAC}
 
 The TLC 7528 is a Dual output parallel input R2R Ladder DAC with a maximum
-sample rate of 10MHz \cite{tlc7528}, and which (should be) is monotonic over the
-entire D/A Conversion Range. The TLC-7528 was the only component chosen, where
-availability was not a factor, but rather it's design. It is the cheapest
-dual R2R Ladder dac which takes \textbf{PARALLEL} input, which is an important
+sample rate of 10MHz \cite{tlc7528}, and which (should be
+\footnote{See Figure \ref{fig:tlc7528_saw_nonlin}}) is monotonic over the
+entire D/A Conversion Range. The TLC-7528 is the only component chosen, where
+availability is not a factor, but rather it's design. It is the cheapest
+dual R2R Ladder DAC which takes \textbf{PARALLEL} input, which is an important
 feature, because the backbone of the project is its parallel bus. Further the
-DAC was developed for audio aplications\cite{tlc7528} which made its use obvious
-and the TLC-7528 was the only IC available as DIP
+DAC was developed for audio aplications\cite{tlc7528}, which made its use 
+obvious. The TLC-7528 was the only IC available as DIP
 \footnote{DIP... Dual Inline Package}, of which the pinout can be seen in Figure
-\ref{fig:tlc7528_pinout}
+\ref{fig:tlc7528_pinout}.
 
 \begin{figure}[H]
 	\centering
@@ -29,7 +30,7 @@ and the TLC-7528 was the only IC available as DIP
 
 \subsubsection{IDT7201 CMOS FIFO Buffer}
 
-The IDT7201 is an asychronous CMOS FIFO, which means that it can be read with
+The IDT7201 is an asychronous CMOS FIFO. That means, that it can be read with
 a completely independant speed from which it is written and vice versa. It has
 9 bit words, which can be seen in Figure \ref{fig:idt7201_pinout}, and can 
 store up to 256 words\cite{idt7201}. It is used as a buffer
@@ -102,7 +103,7 @@ Based on the descriptions in the datasheets the schematic in figure
 
 Diodes D1 through D4 are used as OR-Gates in conjunction with R1 and R2 to
 generate the $\lnot MODRD$ and $\lnot MODWR$ signals for the D Flip-Flop
-\footnote{74HC374\cite{74hc374}} and FIFO respectively, by these formulas: 
+\footnote{74HC374\cite{74hc374}} and FIFO respectively by these formulas: 
 
 $\lnot MODRD = \lnot RD \lor \lnot MS2$
 
@@ -111,22 +112,23 @@ $\lnot MODWR = \lnot WR \lor \lnot MS2$
 On a read access the output enable of the D-Latch becomes low, which writes
 the status bits of the FIFO onto the data bus. C1, C2 and C3 are for stability
 reasons and are good practice similar to the UART module. 74HC00 is a quad 
-NAND-Gate\cite{74hc00} which is only used for inversion, chosen, like the
+NAND-Gate\cite{74hc00}, which is only used for inversion, chosen, like the
 74HC374, for availability reasons. The A part of the NAND-Gate inverts the $MR$
 signal from the bus to a $\lnot MR$ signal, as the FIFOs reset is low active.
 The B part of the NAND-Gate inverts the FIFO Empty flag. It's output is
-connected to the $\lnot WR$ input of the DAC, which means that the DAC doesn't
+connected to the $\lnot WR$ input of the DAC, which means, that the DAC doesn't
 convert the input anymore, if the FIFO Empty flag is set to low.
 
 The NE555 generates the audio clock signal, which should be the double of
-44.1kHz\footnote{Because we have 2 output channels} as 44.1kHz is the standard
-samling rate of CD-Audio\cite{iec60908}. Resistors R9 and R10 togehter with C7
+44.1kHz\footnote{Because we have 2 output channels}, as 44.1kHz is the standard
+samling rate of CD-Audio\cite{iec60908} and 2 channels need to be sampled. 
+Resistors R9 and R10 togehter with C7
 form the Oscillator part of the NE55. C4 is for stability reasons and doesn't
 define the frequency of the oscillator.
 
 The generated clock is used for the $\lnot RD$ of the FIFO and inverted on the
 DAC, which makes the data available on the output before being stored into the
-DAC as it receives the signal to store the data after the FIFO makes it
+DAC, as it receives the signal to store the data, after the FIFO makes it
 available on the bus.
 
 The DAC is operated in voltage mode, as described in Figure \ref{fig:tlc7528_volt},
@@ -142,7 +144,7 @@ $f_C = \frac{1}{2\pi R C} = \frac{1}{2\times \pi\times 10K\Omega\times  100\mu F
 
 which should cover the hearable spectrum. The high pass was needed to generate
 a positive and negative half of the wave form, as the DC-Offset with a frequency
-of 0Hz is orders of magnitudes lower than the $f_C$ of the highpass gets 
+of 0Hz is orders of magnitudes lower, than the $f_C$ of the highpass gets 
 filtered away.
 
 R7 and R8 have been installed in order to unload the capacitors after device
@@ -303,7 +305,7 @@ The look-up table has a size of 256, which is the maximum value an 8 bit integer
 can take. This size was chosen to make operation faster as it only takes
 one cycle to load an array value into a register and another one to store it
 into the GPIO register. The sine table in further examples was pre-genrated on
-the compiling host to reduce startup time. The mothod shown in listing 
+the compiling host to reduce startup time. The method shown in listing 
 \ref{lst:dac_sine_lut} is not fast due to the lack of a floating point unit
 on the AVR. \cite{atmega2560}
 
@@ -344,12 +346,12 @@ on the AVR. \cite{atmega2560}
 
 \subsubsection{Addressing DACA and DACB}
 
-The DAC used has 2 output channels which can be selected by the 
+The DAC used has 2 output channels, which can be selected by the 
 $\lnot DACA/DACB$ pin as seen in figure \ref{fig:tlc7528_pinout}. This pin was
 mapped to bit 0 of the address bus in order to make use of it. Bit 8 on the fifo
-was used to store the bit. It was not implemented with half the bus clock to
+was used to store the bit. It is not implemented with half the bus clock to
 make both channels independent of each other. This however uses more time on the
-backend because it means the fifo is used up at twice the speed. No current
+backend because it means the FIFO is used up at twice the speed. No current
 example makes use of this, but it may be used in future examples and
 implementations on this unit.
 

sections/DP/fpga_interface/main.tex

@@ -1,13 +1,14 @@
 \subsection{FPGA to Hardware interface}
 
 To make the Hardware work with the FPGA's 3.3V I/O, level shifter have been
-installed and a FPGA module was built. This module maps the IO/Pins in a similar
+installed, and a FPGA module was built. This module maps the I/O Pins in a 
+similar
 way to the ATMega 2560 used in examples before. The bidirectional 5V<->3.3V
-logic level converters have been obtained on amazon, and have not been well
-documented. Their functionality has been tested and verified in both directions,
+logic level converters have been obtained on amazon, and are not well
+documented. Their functionality is tested and verified in both directions,
 which can be seen in figures \ref{fig:3v35v} and \ref{fig:5v3v3}. The schematic
-has also been determined through measurements with a multimeter and the 
-schematic in figure \ref{fig:schem_lvlshift} shows similar resistor values in
+was determined through measurements with a multimeter, and the 
+schematic in Figure \ref{fig:schem_lvlshift} shows similar resistor values in
 the same configuration \cite{lvlshift}.
 
 \begin{figure}[H]
@@ -31,8 +32,8 @@ the same configuration \cite{lvlshift}.
 	\label{fig:3v35v}
 \end{figure}
 
-The in figure \ref{fig:3v35v} shown output on the HV side, corresponds with the
-schematics in figure \ref{fig:schem_lvlshift} where it can be seen that the
+The in Figure \ref{fig:3v35v} shown output on the HV side corresponds with the
+schematics in Figure \ref{fig:schem_lvlshift}, where one can see, that the
 resistor R2 is loading the bus capacitance to a 5V high state.
 
 \begin{figure}[H]
@@ -67,7 +68,7 @@ resistor R2 is loading the bus capacitance to a 5V high state.
 
 During an attempt to measure wether the level shifters in the final module were
 working, a measurement between the LV and the HV side showed only a difference
-of 0.7V. After some troubleshooting, it was found that the Analog Discovery has
+of 0.7V. After some troubleshooting, it was found, that the Analog Discovery has
 clamping diodes against the 3.3V rail shown in figure \ref{fig:ad2_diode}. These
 diodes produce the 0.7V offset and prevent the parallel bus from rising to
 5V when a digial I/O pin of the Analog Discovery 2 is connected to the bus.

sections/DP/textadv/main.tex

@@ -9,11 +9,12 @@ one developed.
 
 \subsubsection{General definitions and pinout of the AVR}
 
-Like the before examples, the textadventure was implemented on an ATMega2560
+Like the examples seen before, the textadventure was implemented on an 
+ATMega2560
 and uses 3 different Registers for transmission: PORTF, PORTK and PORTL for
 address bus, data bus and control bus respectively, as can be seen in listing
 \ref{lst:textadv-avr.h}
-\newpage
+
 \lstinputlisting[language=C,frame=trBL,
 	breaklines=true, breakautoindent=true, formfeed=\newpage,
 	label={lst:textadv-avr.h}, caption={The avr.h header file},
@@ -25,8 +26,9 @@ RD_SHIFT, CS_UART_SHIFT and CS_DAC_SHIFT are used to indicate the position of
 the corresponding control lines inside the control bus register. All other
 shift values are the same bitordering in input as in output.
 
-The BUS_HOLD_US is used to tell the avr how many microseconds it takes for the
-data bus to be latched into input register of the devices on write or how long
+The macro BUS_HOLD_US is used to tell the AVR how many microseconds it takes for
+the
+data bus to be latched into input register of the devices on write, or how long
 it takes for the data bus to become stable on read. A delay of less than 1
 microsecond is not possible due to limitations of the AVR and the bus capacity,
 which increases the BER\footnote{BER...Bit Error Ratio} to a level which effects
@@ -48,7 +50,7 @@ respective modules for updates as can be seen in listings
 \ref{lst:textadv-routine-uart} and \ref{lst:textadv-routine-dac}. When a
 character is received, it is stored inside a bufer array and regular operation
 continues. If the $\lnot EF$ status bit is set in a read from the dac, the
-feed\_dac function is called which stores 256 bytes into the DAC and regular
+feed\_dac function is called, which stores 256 bytes into the DAC, and regular
 operation continues.
 
 \lstinputlisting[language=C,frame=trBL,
@@ -72,9 +74,9 @@ operation continues.
 \subsubsection{Program execution path}
 
 On microprocessors it is required to not leave a return path for programs, as
-a return path would lead to the microcontroller either resetting, or seicing to
+a return path would lead to the microcontroller either resetting or seicing to
 work until the next power cut. Therefore the program performs all it's tasks in
-an infinte loop. This loop can be seen in listing \ref{lst:textadv-routine} and
+an infinite loop. This loop can be seen in listing \ref{lst:textadv-routine} and
 in figure \ref{fig:textadv_pexfl}.
 
 \begin{figure}[H]
@@ -92,15 +94,15 @@ The DAC can produce any waveform described by 8 bit unsigned PCM code. Though
 possible to feed predefined waveforms into the DAC, the AVR doesn't have enough
 onboard memory to store more than a few seconds of these waveforms.
 
-For example to store one second of 8 bit unsigned PCM Code at 2 times 44.1KHz 
-sampling rate of the  DAC, the AVR would have to store 
+For exampl: To store one second of 8 bit unsigned PCM Code at 2 times 44.1KHz 
+sampling rate of the DAC the AVR would have to store 
 $s = 2 \times 44100\frac{Bytes}{s}*1s = 2\times 44100 Bytes = 88.2KB$, but it
-has only a total of 256KB of onboard flash\cite{atmega2560} which makes for a
+has only a total of 256KB of onboard flash\cite{atmega2560} which results in a
 total track lengh of $ t = \frac{256KB}{88.2\frac{KB}{s}} = 2.9s$ with only 
 one track.
 
-Therefore the AVR generates the audio on runtime. To do that it has 6 builtin
-modes in which it can run, as can be seen in listing
+Therefore the AVR generates the audio during runtime. In order to do that it has
+6 modes in which it can operate, as can be seen in Listing
 \ref{lst:textadv-dac-modes}:
 
 \begin{enumerate}
@@ -129,7 +131,7 @@ To perform these tasks the DAC takes two parameters, again seen in listing
 \ref{lst:textadv-dac-modes}:
 \begin{itemize}
 	\item{A frequency deviation:}
-		Used to tell the dac how much the desired frequency deviates 
+		Used to tell the DAC how much the desired frequency deviates 
 		from the base frequency of each waveform.
 	\item{A mode:}
 		Used to tell it which waveform to generate
@@ -154,9 +156,9 @@ a waveform at a specific frequency played for a specific time. To perform the
 specific time functionality independant of DAC speed, an ISR
 \footnote{ISR...Interrupt Service Routine} on the AVR was used to change to
 the next tone every millisecond. A track is an array of tones with an end marker
-tone at the end which is a tone with a length of 0ms. The end marker tone tells
-the ISR to reset to the initial tone. The ISR can be seen in listing 
-\ref{lst:textadv-isr} and the sound update function, which actually updates the
+tone at the end, which is a tone with a length of 0ms. The end marker tone tells
+the ISR to reset to the initial tone. The ISR can be seen in Listing 
+\ref{lst:textadv-isr}, and the sound update function, which actually updates the
 current tone and is responsible for playing a track in listing 
 \ref{lst:textadv-upsnd}. The output of an example track can be seen in 
 figures \ref{fig:textadv_track_ex1} and \ref{fig:textadv_track_ex2}.
@@ -222,8 +224,8 @@ figures \ref{fig:textadv_track_ex1} and \ref{fig:textadv_track_ex2}.
 To switch tracks on different actions, there is a map of tracks associated with
 rooms. Every room has an associated track, where the association can change on
 actions performed, which allows for a game atmosphere change. Track changes are
-performed outside the ISR, which could theoretically result in a race condition
-where the ISR would load a faulty track for 1ms if the track change was not
+performed outside the ISR, which could theoretically result in a race condition,
+where the ISR would load a faulty track for 1ms, if the track change was not
 performed fast enough, but this is prevented by disabling global interrupts
 during a track change.
 
@@ -232,21 +234,23 @@ during a track change.
 \subsubsection{Command structure and parsing}
 As in other text adventures \cite{dunnet} a command consits of one line of
 input terminated by a newline or line feed character \textbackslash n.
-The carriage return character which is sometimes transmitted with a line
-feed character is not parsed in this text adventure. Incoming character
-parsing can be seen in listings \ref{lst:textadv-routine-uart} and 
+The carriage return character, which is sometimes transmitted with a line
+feed character, is not parsed in this text adventure. Incoming character
+parsing can be seen in Listings \ref{lst:textadv-routine-uart} and 
 \ref{lst:textadv-ingest}.
 
-As one command is parsed each part is required to be separated by an empty
-space character which is ascii code 32 \cite{ascii}. The first part of the given
+As one command is parsed, each part is required to be separated by an empty
+space character, which is ascii code 32 \cite{ascii}. The first part of the 
+given
 input is then compared to an array of actions a user can perform, for example
-use or search, as can be seen in listing \ref{lst:textadv-parsecmd}
+use or search, as can be seen in Listing \ref{lst:textadv-parsecmd}
 
 In listing \ref{lst:textadv-routine-uart} the comment echo back can be seen. The
-write\_char function before it writes the last received character back to the
-terminal which sent it. This is done to write what the user typed out to the
-terminal as otherwise it would not be seen what has been typed on any VT100
-compatiable terminal\cite{vt100} or terminal emulator. 
+write\_char function, writes it's parameter to the user., in this case the 
+input sent by the user.
+This is done to write what the user typed out to the
+terminal as otherwise one would not be able to see  what has been typed on any 
+VT100 compatiable terminal\cite{vt100} or terminal emulator. 
 
 \lstinputlisting[language=C,frame=trBL,
 	breaklines=true, breakautoindent=true, formfeed=\newpage,
@@ -254,12 +258,12 @@ compatiable terminal\cite{vt100} or terminal emulator.
 	columns=flexible, style=cstyle, firstline=73, lastline=81]
 		{code/textadv/src/game.c}
 
-The in listing \ref{lst:textadv-ingest} shown branch overrides the last received
-character with 0x00 which is ascii NUL and decrements the buffer pointer by one
-if the received character was 0x7F. 0x7F is the ADCII DELETE character
-\cite{ascii} which instructs the receiving end that the last received character
+The in Listing \ref{lst:textadv-ingest} shown branch overrides the last received
+character with 0x00, which is ascii NUL, and decrements the buffer pointer by 
+one if the received character was 0x7F. 0x7F is the ADCII DELETE character
+\cite{ascii} which instructs the receiving end, that the last received character
 was a mistake and should be purged. This is also what a vt100 compiant terminal
-emulator sends when the backspace or delete key is pressed \cite{vt100}.
+emulator sends, when the backspace or delete key is pressed \cite{vt100}.
 
 \lstinputlisting[language=C,frame=trBL,
 	breaklines=true, breakautoindent=true, formfeed=\newpage,
@@ -269,15 +273,15 @@ emulator sends when the backspace or delete key is pressed \cite{vt100}.
 
 \subsubsection{Command parameters}
 
-Command paramters are interpreted as the string that follows the action
+Command paramters are interpreted as the string, that follows the action
 and the space behind it. As can be seen in the case for ACTION\_USE in
-listing \ref{lst:textadv-perfact} the use item function is passed the 
+Listing \ref{lst:textadv-perfact}, the use item function is passed the 
 command buffer\footnote{which is an address in memory} plus the length of the
 entered command plus one for the space. So the string starting at the passed
 address should match the start address of the parameter. If no parameter is
 supplied, the address should point to a character containing ASCII NUL, which
-marks the end of a string, bcause after comand parsing the string is overwritten
-with zeros as seen in listing \ref{lst:textadv-parsecmd}.
+marks the end of a string, because after command parsing, the string is 
+overwritten with zeros as seen in Listing \ref{lst:textadv-parsecmd}.
 
 \lstinputlisting[language=C,frame=trBL,
 	breaklines=true, breakautoindent=true, formfeed=\newpage,
@@ -288,7 +292,7 @@ with zeros as seen in listing \ref{lst:textadv-parsecmd}.
 \subsection{Gameplay}
 
 The game itself plays like a regular game with limtations set in direction.
-Playeras can search for items in each room and grab the found items as can be
+Players can search for items in each room and grab the found items as can be
 seen in figure \ref{fig:tetadv_gameplay}. The general gamplay is perfomred via
 altering the map data and the strings output to the user. 
 
@@ -301,45 +305,45 @@ altering the map data and the strings output to the user.
 
 \subsubsection{Memory constraints}
 
-The AVR has 8kB of internal SRAM which are used for stack and heap
-\cite{atmega2560}. During the build of the program an ELF file can be obtained
+The AVR has 8kB of internal SRAM, which are used for stack and heap
+\cite{atmega2560}. During the build of the program an ELF file can be obtained,
 which contains infromation on the programs structure and memory usage on boot.
-Strings and variables are contained within the .data section of the elf file,
+Strings and variables are contained within the .data section of the elf file
 and loaded into memory during boot\cite{elf}. This is done for integer
-variables, as well as for strings, which makes the use of strings limited not
+variables as well as for strings, which makes the use of strings limited not
 to the flash size but to the RAM size of the AVR. To save memory, sound tracks
 as well as the sine and noise table have been put into program space with the 
 PROGMEM attribute as described by the avr-libc documentation\cite{progmem}. 
 In listing \ref{lst:textadv-dac-gen} a read from program memory can be seen in
-the noise and sine modes. Strings have not been put into programmspace as this
+the noise and sine modes. Strings have not been put into programmspace, as this
 would require each string to be declared independantly and then be put into
-arrays\cite{progmem} as is done now, which would make the code much less
-readable and increase overhead As well as make the usage of buffers nescessary
+arrays\cite{progmem} as is done now. Which would make the code much less
+readable and increase overhead as well as make the usage of buffers nescessary
 in order for the override of the printf function to work.
 
 \subsubsection{Story}
 
-The basics of the storyline are that you wake up in the middle of a forest and
+The basics of the storyline are, that you wake up in the middle of a forest and
 don't remember anything. You have to get through the forest to an old house,
-while having to get rid of a bear which is blocking the way. Inside the house
-you have to get a computer to start. The game then proceeds to get recursive and
-your goal is to break out of the recursion.
+while having to get rid of a bear, which is blocking the way. Inside the house
+you have to get a computer to start. The game then proceeds to get recursive, 
+and your goal is to break out of the recursion.
 
 \subsubsection{Recursion}
 
 The game, when performing the recursion, resets your inventory and internal
-state machines, before putting you back to the starting point. However by 
+state machines, before putting you back to the starting point. However, by 
 altering the orientation of rooms, altering the list of items found inside rooms
-and by altering the texts output by the game, the atmosphere can be changed, and
+and by altering the texts output by the game, the atmosphere and
 the outcome changed.
 
 \subsubsection{Computer State Machine}
 
 One example of a state machine inside the game is the computer inside the
-old-house. The computer needs three items: a keyboard to type on, something to
+old-house. The computer needs three items: A keyboard to type on, something to
 boot from, for example a floppy disk, and a screwdriver to start it. The state
-machine implementation can be seen in listing \ref{lst:textadv-fsm} and the
-state diagram in figure \ref{fig:textadv_compfsm}.
+machine implementation can be seen in Listing \ref{lst:textadv-fsm} and the
+state diagram in Figure \ref{fig:textadv_compfsm}.
 
 \lstinputlisting[language=C,frame=trBL,
 	breaklines=true, breakautoindent=true, formfeed=\newpage,

sections/abstract.tex

@@ -6,7 +6,7 @@ anschaulich den
 Aufbau eines Computersystems in Hard- und Software zu veranschaulichen
 sowie diesen zu erklären. Dafür wurde auf einem XILINX FPGA ein RISC-V32I 
 Prozessor in VHDL
-implementiert sowie diverse Parallelbus gebundene Hardwareperipherie entwickelt
+implementiert, sowie diverse Parallelbus-gebundene Hardwareperipherie entwickelt
 und gebaut. Als Harwareperipherie wurde ein 8-Bit 2-Kanal DAC und eine serielle
 Schnittstelle mit TIA-/EIA-232 Pegeln gewählt. Der Prozessor implementiert das
 RISC-V32I base instruction set. Aufgrund der starken Verwendung von Englisch im
@@ -17,14 +17,14 @@ Menschen mit einem grundlegenden Verständnis für Elektronik sowie der Hardware
 Beschreibungssprache VHDL verständlich sein.
 \end{otherlanguage}
 \\\\
-This diploma thesis deals with the operation of processors and their 
-corresponding peripherals in modern and traditional forms. It attempts to
+This diploma thesis demonstrates the operation of processors and their 
+corresponding peripherals, both in modern and traditional forms. It attempts to
 illustrate the structure of a computer system in hard- and software. To reach
-this goal a RISC-V32I processor has been implemented in VHDL on a XILINX FPGA
-as well as some peripherals bound to the parallel bus. These peripherals
-include a 2-channel 8-bit Digital to analog converter as well as a TIA-/EIA-232
+this goal, a RISC-V processor was implemented in VHDL on a Xilinx FPGA and some
+parallel bus peripherals were designed using discrete hardware. These peripherals
+include a 2-channel 8-bit digital-to-analog converter as well as a TIA-/EIA-232
 compliant serial interface. Due to the common use of english in the hardware and
-software engineering field this thesis is written in english, which
-enhances readability as well. The written documentation should be comprehensible
-for everyone with a basic understanding of electronics as well as the
+software engineering field, and in a resulting effort to increase readability,
+this thesis is written in English. The written documentation should be comprehensible
+for anyone with a basic understanding of electronics as well as the
 hardware description language VHDL.

sections/fpga-development.tex

@@ -0,0 +1,81 @@
+\documentclass[../../Diplomschrift.tex]{subfiles}
+
+\begin{document}
+\section{FPGA Development}
+
+The project started out with the desire to build a CPU from scratch. Examples such as The NAND Game~\cite{nandgame} and Ben Eater's Breadboard Computer series~\cite{breadboard_computer} served as inspirations and guidance during development.
+
+At first, a design similar to Ben Eater's, consisting solely of discrete integrated circuits, was considered, but soon discarded in favor of an FPGA-based design. Designing the logic alone was a difficult task, implementing it in discrete hardware would have pushed the project far over the allotted maximum development time.
+
+RISC-V was chosen as the instruction set architecture for the processor. Its modular design with a very small base instruction set makes it easy to implement a basic processor that is still fully compatible with existing software and toolchains.
+
+As a starting point, a Terasic DE0 development board\footnote{\url{https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=364}} containing an Altera Cyclone III\footnote{\url{https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iii.html}} FPGA was borrowed from the school's inventory. It was used to implement a first version of the core.
+
+The only method of synthesis for Altera devices is to use the proprietary Quartus IDE. However, the last version of Quartus to support the Cyclone III series of FPGAs (version 13.1) had already been out of date for several years at the start of the project. Because of this and the increasing resource demand of the developing core, an Arty A7-35T development board\footnote{\url{https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/}} with a Xilinx Artix-7\footnote{\url{https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html}} FPGA was ordered from Digilent.
+
+A comparison between the two FPGAs themselves can be seen in \autoref{tab:fpga-comparison}, a comparison between the peripherals on the development boards in \autoref{tab:devboard-comparison}.
+
+\begin{table}[h]
+\centering
+\begin{tabular}{l|r|r}
+\toprule
+               & Altera EP3C16 & Xilinx XC7A35T \\
+\midrule
+Logic Elements & 15000 & 33280 \\
+Multipliers    &    56 &    90 \\
+Block RAM (kb) &   504 &  1800 \\
+PLLs           &     4 &     5 \\
+Global clocks  &    20 &    32 \\
+\bottomrule
+\end{tabular}
+\caption{Comparison between Altera and Xilinx FPGAs}
+\label{tab:fpga-comparison}
+\end{table}
+
+\begin{table}[h]
+\centering
+\begin{tabular}{l|r|r}
+\toprule
+         & Terasic DE0 & Digilent Arty A7-35T \\
+\midrule
+Switches &           10 & 4 \\
+Buttons  &            3 & 4 \\
+LEDs     & 10 + 4x 7-segment & 4 + 3 RGB \\
+GPIOs    &        2x 36 & 4x PMOD + chipKIT \\
+Memory   &    8MB SDRAM & 256MB DDR3L \\
+Others   & SD card, VGA & Ethernet \\
+\bottomrule
+\end{tabular}
+\caption{Comparison between the peripherals on Terasic and Digilent FPGA development boards}
+\label{tab:devboard-comparison}
+\end{table}
+
+While the Digilent board offers fewer IO options, the DDR3 memory can be interfaced using Free memory cores and allows for much larger programs to be loaded, possibly even a full operating system. The missing VGA port has been substituted by an HDMI-compatible DVI interface that is accessible through one of the high-speed PMOD connectors.
+
+\subsection{Tooling}
+
+FPGA design is done using a Hardware Description Language (HDL). The two most well-known HDLs are Verilog and VHDL (VHSIC (Very high speed integrated circuit) HDL). As part of our studies at HTL, we exclusively worked with VHDL. For this reason, and because VHDL offers a strong type system~\cite{vhdl-types}, it was selected as the language of choice for the project.
+
+To refresh the reader's memory on the VHDL language, and as a quick guide for the tools involved in this project, see Appendix~\ref{app:vhdl-intro}.
+
+\subsubsection{Vendor Tools}
+
+The conventional way to work with FPGA designs is to use the FPGA vendor's development solution for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution.
+
+Vendor tools are usually free-of-charge for basic usage, but this also means there is no guaranteed support. During the development of this project, several bugs and missing features were found in vendor tools that required workarounds.
+
+\subsubsection{Free Software Tools}
+
+A somewhat recent development is the creation of Free Software FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys~\cite{yosys-paper, yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series. Since then, both yosys and place-and-route tools like nextpnr~\cite{nextpnr} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route.
+
+Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing \emph{from} VHDL code and synthesizing \emph{to} Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released ghdlsynth-beta~\cite{ghdlsynth-beta}, a bridge between GHDL~\cite{ghdl} and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr~\cite{nextpnr-xilinx}. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}~\cite{prjxray}.
+
+With these two pieces in place, the project was switched over to a completely Free toolchain, removing any depencies on vendor tools:
+
+\begin{itemize}
+ \item yosys, with ghdl as a frontend for processing VHDL and ghdlsynth as a bridge between them, is used to synthesize the design
+ \item nextpnr-xilinx, together with the Project X-Ray database, is used for place-and-route
+ \item tools from Project X-Ray are used to convert the routed design to a bitstream
+ \item openFPGALoader is used to transfer the bitstream to the FPGA via JTAG
+\end{itemize}
+\end{document}

sections/intro.tex

@@ -1,22 +1,35 @@
 In early 2018, more than a year before the official start of the project, after
 searching for a subject for the diploma thesis, the idea of building a computer
-from scratch has come up. Multiple suggestions on how to implement it and the
-scope of the project were gathered. Originally the goal of the project was to
-have a computer which would consist of seperate plug-in cards on each of which
-one instruction would reside. This would debunk the mystery behind the ``black
-box`` which processors are today.
+from scratch had come up. Multiple suggestions on how to implement it and the
+scope of the project were gathered. Originally, the goal was to
+design a computer consisting of seperate plug-in cards, one instruction would
+residing on each. This would open up the ``black box`` of modern processor
+design, showing the basic components at a macroscopic scale.
 
-Most processors today are only documented on the execution of their programs and
-not on their internals. The projects aim was later redirected, due to concerns
-about the difficulty of the project, to build a processor in VHDL instead. After
-several months of implementation time the project was split into two parts: the
-peripherals and the core processor. During the development processes and after
-rememberingthe original goal to make a processor understandable, the
-peripherals changed from being implemented in VHDL back to hardware, which came
-with increased work but would result in a far more understandable final product.
+The project's aim was later
+redirected due to concerns about difficulty, and an FPGA-based design was opted
+for instead. After
+several months of implementation time, the project was split into two parts: the
+peripherals and the core processor. During the development process, and to get
+back to the original goal of making a processor understandable, the
+peripherals changed from being implemented in VHDL back to hardware.
+This increased the required effort, but would result in a far more
+understandable final product.
 
-The decision for a RISC-V based processor was made at the beginning of the 
-project, because the core architecture is well documented, modular and almost
-any part not implemented inside the processor(if not specifically
-required by the software) should be emulateable in software.
+The decision to use a RISC-V based processor was made at the beginning of the 
+project because the core architecture is well documented and modular, and because
+almost any feature not implemented inside the processor can be emulated using
+software instead.
 
+\subsection{Free software}
+\label{sec:free-software}
+
+For most of today's processors, documentation only exists on the execution of
+programs (the runtime), not for their internals. In order the have the biggest
+possible educational potential, this project is entirely "Free as in speech":
+All involved software and hardware designs, as well as all the tools and
+utilities required to create them, comply with the Free Software Foundation's
+definition for Free software~\cite{fsf-definition}. They give the users the
+rights to share, study and modify them at their will. In this thesis, the
+capital-F ``Free'' is used to refer to this definition rather than the
+meaning of ``free of charge'' or ``gratis''.

sections/result.tex

@@ -1,12 +1,13 @@
 The project is fully implemented with all functionality originally targeted.
-The system has been tested and verified. All example codes have been
+The system has been tested and verified. All example code has been
 documented and tested. Hardware implementations were created using
-Free software programs, while the RISC-V processor can be compiled with a Free
-toolchain. The completed project can be found on the USB stick, which accompanies
+Free software\footnote{See \autoref{sec:free-software}} programs, while the
+RISC-V processor can be compiled with a Free
+toolchain. The completed project can be found on the USB stick which accompanies
 this thesis, or in the git repositories at 
 \url{https://git.it-syndikat.org/tyrolyean/dipl.git} and 
 \url{https://gitlab.com/YARM-project/}. The completed hardware peripherals can
-be seen in Figure \ref{fig:all_mod}
+be seen in \autoref{fig:all_mod}.
 
 \begin{figure}[H]
 	\centering

sections/soc/soc.tex

@@ -1,94 +1,13 @@
 \documentclass[../../Diplomschrift.tex]{subfiles}
 
 \begin{document}
-\section{Development History}
+\section{SoC Peripherals}
 
-The project started out with the desire to build a CPU from scratch. Examples such as The NAND Game~\cite{nandgame} and Ben Eater's Breadboard Computer series~\cite{breadboard_computer} served as inspirations and guidance during development.
-
-At first, a design similar to Ben Eater's consisting solely of discrete integrated circuits was considered, but soon discarded in favor of an FPGA-based design. Designing the logic alone was a difficult task, implementing it in discrete hardware would have pushed the project far over the allotted maximum development time.
-
-RISC-V was chosen as the instruction set architecture for the processor. Its modular design with a very small base instruction set make it easy to implement a basic processor that is still fully compatible with existing software and toolchains.
-
-As a starting point, a Terasic DE0 development board\footnote{\url{https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=364}} containing an Altera Cyclone III\footnote{\url{https://www.intel.com/content/www/us/en/products/programmable/fpga/cyclone-iii.html}} FPGA was borrowed from the school's inventory. It was used to implement a first version of the core.
-
-The only method of synthesis for Altera devices is to use the proprietary Quartus IDE. However, the last version of Quartus to support the Cyclone III series of FPGAs (version 13.1) had already been out of date for several years at the start of the project. Because of this and the increasing resource demand of the developing core, an Arty A7-35T development board\footnote{\url{https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/}} with a Xilinx Artix-7\footnote{\url{https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html}} FPGA was ordered from Digilent.
-
-A comparison between the two FPGAs themselves can be seen in \autoref{tab:fpga-comparison}, a comparison between the peripherals on the development boards in \autoref{tab:devboard-comparison}.
-
-\begin{table}[h]
-\centering
-\begin{tabular}{l|r|r}
-\toprule
-               & Altera EP3C16 & Xilinx XC7A35T \\
-\midrule
-Logic Elements & 15000 & 33280 \\
-Multipliers    &    56 &    90 \\
-Block RAM (kb) &   504 &  1800 \\
-PLLs           &     4 &     5 \\
-Global clocks  &    20 &    32 \\
-\bottomrule
-\end{tabular}
-\caption{Comparison between Altera and Xilinx FPGAs}
-\label{tab:fpga-comparison}
-\end{table}
-
-\begin{table}[h]
-\centering
-\begin{tabular}{l|r|r}
-\toprule
-         & Terasic DE0 & Digilent Arty A7-35T \\
-\midrule
-Switches &           10 & 4 \\
-Buttons  &            3 & 4 \\
-LEDs     & 10 + 4x 7-segment & 4 + 3 RGB \\
-GPIOs    &        2x 36 & 4x PMOD + chipKIT \\
-Memory   &    8MB SDRAM & 256MB DDR3L \\
-Others   & SD card, VGA & Ethernet \\
-\bottomrule
-\end{tabular}
-\caption{Comparison between the peripherals on Terasic and Digilent FPGA development boards}
-\label{tab:devboard-comparison}
-\end{table}
-
-While the Digilent board offers fewer IO options, the DDR3 memory can be interfaced using Free memory cores and allows for much larger programs to be loaded, possibly even a full operating system. The missing VGA port has been substituted by an HDMI-compatible DVI interface that is accessible through one of the high-speed PMOD connectors.
-
-\section{FPGA Tooling}
-
-FPGA design is done using a Hardware Description Language (HDL). The two most well-known HDLs are Verilog and VHDL (VHSIC (Very high speed integrated circuit) HDL). As part of our studies at HTL, we exclusively worked with VHDL. For this reason, and because VHDL offers a strong type system~\cite{vhdl-types}, it was selected as the language of choice for the project.
-
-To refresh the reader's memory on the VHDL language, and as a quick guide for the tools involved in this project, see Appendix~\ref{app:vhdl-intro}.
-
-\subsection{Vendor Tools}
-
-The conventional way to work with FPGA designs is to use the FPGA vendor's development solution for simulation, synthesis and place-and-route. All of these tools are proprietary software specialized to a certain FPGA manufacturer, so a change of hardware also requires changing to a completely different software solution.
-
-Vendor tools are usually free-of-charge for basic usage, but this also means there is no guaranteed support. During the development of this project, several bugs and missing features were found in vendor tools that required workarounds.
-
-\subsection{Free Software Tools}
-
-A somewhat recent development is the creation of Free Software\footnotemark{} FPGA toolchains. A breakthrough was achieved by Claire (formerly Clifford) Wolf in 2013 with yosys~\cite{yosys-paper, yosys}, a feature-complete Verilog synthesis suite for Lattice's \texttt{iCE40} FPGA series.
-    \footnotetext{``Free Software'' refers to software that grants its user the freedom to share, study and modify it - see \url{https://www.fsf.org/about/what-is-free-software}.}
-Since then, both yosys and place-and-route tools like nextpnr~\cite{nextpnr} have matured, however Lattice's iCE40 and ECP5 remained the only supported FPGA architectures for place-and-route.
-
-Thus, two obstacles remained for Free toolchains to be viable for this project: synthesizing \emph{from} VHDL code and synthesizing \emph{to} Artix-7 FPGAs. During the development of the project, both of these were solved: Tristan Gingold released ghdlsynth-beta~\cite{ghdlsynth-beta}, a bridge between GHDL~\cite{ghdl} and yosys allowing VHDL to be synthesized just the same as Verilog, and Dave Shah added Xilinx support to nextpnr~\cite{nextpnr-xilinx}. The latter was preceded by many months of volunteer work reverse-engineering the Xilinx bitstream format as part of \textit{Project X-Ray}~\cite{prjxray}.
-
-With these two pieces in place, the project was switched over to a completely Free toolchain, removing any depencies on vendor tools:
-
-\begin{itemize}
- \item yosys, with ghdl as a frontend for processing VHDL and ghdlsynth as a bridge between them, is used to synthesize the design
- \item nextpnr-xilinx, together with the Project X-Ray database, is used for place-and-route
- \item tools from Project X-Ray are used to convert the routed design to a bitstream
- \item openFPGALoader is used to transfer the bitstream to the FPGA via JTAG
-\end{itemize}
-
-\section{Peripherals}
-
-The complete FPGA design consists not only of the CPU core, but a number of components that allow it to operate and communicate with the outside environment. They are connected using a shared 32-bit bus.
+The complete FPGA design consists not only of the CPU core, but a number of components that allow it to operate as well as to communicate with the outside environment. They are connected to the core using a shared 32-bit bus.
 
 \subsection{UART}
 
-The easiest way to communicate with an embedded system is usually through a serial interface. To ensure the best compatibility with existing software, a National Semiconductor 16550 UART was reimplemented from scratch instead of creating a new design. Thus, the modules's functionality and design can be found in the 16550's datasheet.
-% TODO ref
+The easiest way to communicate with an embedded system is usually through a serial interface. To ensure the best compatibility with existing software, a National Semiconductor 16550 UART was reimplemented from scratch instead of creating a new design. Thus, the modules's functionality and design can be found in the 16550's datasheet~\cite{pc16550}.
 
 \subsection{DVI graphics}
 

sections/texput.log

@@ -1,21 +0,0 @@
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-entering extended mode
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-**main.tec
-
-! Emergency stop.
-<*> main.tec
-            
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-
- 
-Here is how much of TeX's memory you used:
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- 66274 words of memory out of 5000000
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