Language improvements
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@ -6,7 +6,7 @@ anschaulich den
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Aufbau eines Computersystems in Hard- und Software zu veranschaulichen
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sowie diesen zu erklären. Dafür wurde auf einem XILINX FPGA ein RISC-V32I
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Prozessor in VHDL
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implementiert sowie diverse Parallelbus gebundene Hardwareperipherie entwickelt
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implementiert, sowie diverse Parallelbus-gebundene Hardwareperipherie entwickelt
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und gebaut. Als Harwareperipherie wurde ein 8-Bit 2-Kanal DAC und eine serielle
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Schnittstelle mit TIA-/EIA-232 Pegeln gewählt. Der Prozessor implementiert das
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RISC-V32I base instruction set. Aufgrund der starken Verwendung von Englisch im
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@ -17,14 +17,14 @@ Menschen mit einem grundlegenden Verständnis für Elektronik sowie der Hardware
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Beschreibungssprache VHDL verständlich sein.
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\end{otherlanguage}
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\\\\
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This diploma thesis deals with the operation of processors and their
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corresponding peripherals in modern and traditional forms. It attempts to
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illustrate the structure of a computersystem in hard- and software. To reach
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this goal a RISC-V32I processor has been implemented in VHDL on a XILINX FPGA
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as well as some peripherals bound to the parallel bus. These peripherals
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include a 2-channel 8-bit Digital to analog converter as well as a TIA-/EIA-232
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This diploma thesis demonstrates the operation of processors and their
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corresponding peripherals, both in modern and traditional forms. It attempts to
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illustrate the structure of a computer system in hard- and software. To reach
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this goal, a RISC-V processor was implemented in VHDL on a Xilinx FPGA and some
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parallel bus peripherals were designed using discrete hardware. These peripherals
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include a 2-channel 8-bit digital-to-analog converter as well as a TIA-/EIA-232
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compliant serial interface. Due to the common use of english in the hardware and
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software engineering field this thesis is written in english, which
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enhances readability as well. The written documentation should be comprehensible
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for everyone with a basic understanding of electronics as well as the
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software engineering field, and in a resulting effort to increase readability,
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this thesis is written in English. The written documentation should be comprehensible
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for anyone with a basic understanding of electronics as well as the
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hardware description language VHDL.
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@ -1,22 +1,23 @@
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In early 2018, more than a year before the official start of the project, after
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searching for a subject for the diploma thesis, the idea of building a computer
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from scratch has come up. Multiple suggestions on how to implement it and the
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scope of the project were gathered. Originally the goal of the project was to
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have a computer which would consist of seperate plug-in cards on each of which
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one instruction would reside. This would debunk the mystery behind the ``black
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box`` which processors are today.
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from scratch had come up. Multiple suggestions on how to implement it and the
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scope of the project were gathered. Originally, the goal was to
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design a computer consisting of seperate plug-in cards, one instruction would
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residing on each. This would open up the ``black box`` of modern processor
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design, showing the basic components at a macroscopic scale.
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Most processors today are only documented on the execution of their programs and
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not on their internals. The projects aim was later redirected, due to concerns
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about the difficulty of the project, to build a processor in VHDL instead. After
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several months of implementation time the project was split into two parts: the
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peripherals and the core processor. During the development processes and after
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rememberingthe original goal to make a processor understandable, the
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peripherals changed from being implemented in VHDL back to hardware, which came
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with increased work but would result in a far more understandable final product.
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The decision for a RISC-V based processor was made at the beginning of the
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project, because the core architecture is well documented, modular and almost
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any part not implemented inside the processor(if not specifically
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required by the software) should be emulateable in software.
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For most of today's processors, documentation only exists for the execution of
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programs (the runtime), not for their internals. The project's aim was later
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redirected due to concerns about difficulty, and an FPGA-based design was opted
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for instead. After
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several months of implementation time, the project was split into two parts: the
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peripherals and the core processor. During the development process, and to get
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back to the original goal of making a processor understandable, the
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peripherals changed from being implemented in VHDL back to hardware.
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This increased the required effort, but would result in a far more
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understandable final product.
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The decision to use a RISC-V based processor was made at the beginning of the
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project because the core architecture is well documented and modular, and because
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almost any feature not implemented inside the processor can be emulated using
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software instead.
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@ -1,12 +1,13 @@
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The project is fully implemented with all functionality originally targeted.
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The system has been tested and verified. All example codes have been
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The system has been tested and verified. All example code has been
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documented and tested. Hardware implementations were created using
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Free software programs, while the RISC-V processor can be compiled with a Free
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toolchain. The completed project can be found on the USB stick, which accompanies
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Free software\footnote{See \autoref{sec:free-software}} programs, while the
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RISC-V processor can be compiled with a Free
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toolchain. The completed project can be found on the USB stick which accompanies
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this thesis, or in the git repositories at
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\url{https://git.it-syndikat.org/tyrolyean/dipl.git} and
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\url{https://gitlab.com/YARM-project/}. The completed hardware peripherals can
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be seen in Figure \ref{fig:all_mod}
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be seen in \autoref{fig:all_mod}.
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\begin{figure}[H]
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\centering
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