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Merge remote-tracking branch 'iteasyndikat/batman-release-20200327' into waschtl

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Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
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Tyrolyean 2020-03-27 12:58:29 +01:00
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6
Diplomschrift.bib
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@ -71,3 +71,9 @@
title = {GTKWave}, title = {GTKWave},
url = {http://gtkwave.sourceforge.net}, url = {http://gtkwave.sourceforge.net},
} }
@online{riscv-compliance,
author = {Jeremy Bennett, Lee Moore},
title = {RISC-V Compliance Task Group},
url = {https://github.com/riscv/riscv-compliance},
}

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Makefile
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@ -27,7 +27,7 @@ entity_headers: $(HEADER_DIRS)
.PHONY: Diplomschrift.pdf .PHONY: Diplomschrift.pdf
Diplomschrift.pdf: $(HEADER_DIRS) Diplomschrift.tex Diplomschrift.pdf: $(HEADER_DIRS) Diplomschrift.tex
latexmk --pdfxe --pdfxelatex="xelatex -interaction=nonstopmode --shell-escape" --use-make Diplomschrift.tex latexmk --pdfxe --pdfxelatex="lualatex -interaction=nonstopmode --shell-escape" --use-make Diplomschrift.tex
.PHONY: clean .PHONY: clean
clean: clean:

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main.aux
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@ -1,4 +1,5 @@
\relax \relax
\providecommand{\transparent@use}[1]{}
\providecommand\hyper@newdestlabel[2]{} \providecommand\hyper@newdestlabel[2]{}
\providecommand\zref@newlabel[2]{} \providecommand\zref@newlabel[2]{}
\bbl@beforestart \bbl@beforestart
@ -18,22 +19,20 @@
\fi} \fi}
\global\let\hyper@last\relax \global\let\hyper@last\relax
\gdef\HyperFirstAtBeginDocument#1{#1} \gdef\HyperFirstAtBeginDocument#1{#1}
\providecommand*\HyPL@Entry[1]{} \providecommand\HyField@AuxAddToFields[1]{}
\HyPL@Entry{0<</S/D>>} \providecommand\HyField@AuxAddToCoFields[2]{}
\babel@aux{english}{} \babel@aux{english}{}
\@writefile{toc}{\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax } \@writefile{toc}{\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax }
\@writefile{lof}{\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax } \@writefile{lof}{\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax }
\@writefile{lot}{\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax } \@writefile{lot}{\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax }
\babel@aux{ngerman}{} \babel@aux{ngerman}{}
\babel@aux{ngerman}{} \babel@aux{ngerman}{}
\HyPL@Entry{1<</S/r>>}
\@writefile{toc}{\contentsline {section}{Gendererklärung}{i}{Doc-Start}\protected@file@percent } \@writefile{toc}{\contentsline {section}{Gendererklärung}{i}{Doc-Start}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{Kurzfassung/Abstract}{ii}{Doc-Start}\protected@file@percent } \@writefile{toc}{\contentsline {section}{Kurzfassung/Abstract}{ii}{Doc-Start}\protected@file@percent }
\babel@aux{ngerman}{} \babel@aux{ngerman}{}
\babel@aux{ngerman}{} \babel@aux{ngerman}{}
\@writefile{toc}{\contentsline {section}{Result}{iii}{Doc-Start}\protected@file@percent } \@writefile{toc}{\contentsline {section}{Result}{iii}{Doc-Start}\protected@file@percent }
\babel@aux{english}{} \babel@aux{english}{}
\HyPL@Entry{6<</S/D>>}
\@writefile{toc}{\contentsline {section}{\numberline {1}Task description}{1}{section.1}\protected@file@percent } \@writefile{toc}{\contentsline {section}{\numberline {1}Task description}{1}{section.1}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {1.1}Hardware}{1}{subsection.1.1}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {1.1}Hardware}{1}{subsection.1.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {2}Hardware peripherials}{2}{section.2}\protected@file@percent } \@writefile{toc}{\contentsline {section}{\numberline {2}Hardware peripherials}{2}{section.2}\protected@file@percent }
@ -41,78 +40,78 @@
\@writefile{lof}{\contentsline {figure}{\numberline {i}{\ignorespaces Atari PBI Pinout;Source: \url {https://www.atarimagazines.com}\relax }}{2}{figure.caption.1}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {i}{\ignorespaces Atari PBI Pinout;Source: \url {https://www.atarimagazines.com}\relax }}{2}{figure.caption.1}\protected@file@percent }
\providecommand*\caption@xref[2]{\@setref\relax\@undefined{#1}} \providecommand*\caption@xref[2]{\@setref\relax\@undefined{#1}}
\newlabel{fig:atari_pbi}{{i}{2}{Atari PBI Pinout;Source: \url {https://www.atarimagazines.com}\relax }{figure.caption.1}{}} \newlabel{fig:atari_pbi}{{i}{2}{Atari PBI Pinout;Source: \url {https://www.atarimagazines.com}\relax }{figure.caption.1}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.1.1}Address Bus}{2}{subsubsection.2.1.1}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.1.1}Address Bus}{3}{subsubsection.2.1.1}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {2.2}Data Bus}{3}{subsection.2.2}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {2.2}Data Bus}{3}{subsection.2.2}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {2.3}Control Bus}{3}{subsection.2.3}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {2.3}Control Bus}{3}{subsection.2.3}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.3.1}Master Reset}{3}{subsubsection.2.3.1}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.3.1}Master Reset}{3}{subsubsection.2.3.1}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.3.2}Write Not}{3}{subsubsection.2.3.2}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.3.3}Read Not}{3}{subsubsection.2.3.3}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.3.4}Module Select 1 and 2 Not}{3}{subsubsection.2.3.4}\protected@file@percent }
\abx@aux@cite{ad2} \abx@aux@cite{ad2}
\abx@aux@segm{0}{0}{ad2} \abx@aux@segm{0}{0}{ad2}
\abx@aux@cite{atmega2560} \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.3.2}Write Not}{4}{subsubsection.2.3.2}\protected@file@percent }
\abx@aux@segm{0}{0}{atmega2560} \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.3.3}Read Not}{4}{subsubsection.2.3.3}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.3.4}Module Select 1 and 2 Not}{4}{subsubsection.2.3.4}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {2.4}Testing and Measurement}{4}{subsection.2.4}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {2.4}Testing and Measurement}{4}{subsection.2.4}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.4.1}Measurements}{4}{subsubsection.2.4.1}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.4.1}Measurements}{4}{subsubsection.2.4.1}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {ii}{\ignorespaces Digilent Analog Discovery 2;Source: \url {https://www.sparkfun.com/}\relax }}{4}{figure.caption.2}\protected@file@percent } \abx@aux@cite{atmega2560}
\newlabel{fig:ad2}{{ii}{4}{Digilent Analog Discovery 2;Source: \url {https://www.sparkfun.com/}\relax }{figure.caption.2}{}} \abx@aux@segm{0}{0}{atmega2560}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.4.2}Testing}{4}{subsubsection.2.4.2}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {ii}{\ignorespaces Digilent Analog Discovery 2;Source: \url {https://www.sparkfun.com/}\relax }}{5}{figure.caption.2}\protected@file@percent }
\newlabel{fig:ad2}{{ii}{5}{Digilent Analog Discovery 2;Source: \url {https://www.sparkfun.com/}\relax }{figure.caption.2}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.4.2}Testing}{5}{subsubsection.2.4.2}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {2.5}Backplane}{5}{subsection.2.5}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {2.5}Backplane}{5}{subsection.2.5}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {iii}{\ignorespaces Layout of the DIN41612 Connectors on the Backplane\relax }}{5}{figure.caption.3}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {iii}{\ignorespaces Layout of the DIN41612 Connectors on the Backplane\relax }}{6}{figure.caption.3}\protected@file@percent }
\newlabel{fig:schem_back_conn}{{iii}{5}{Layout of the DIN41612 Connectors on the Backplane\relax }{figure.caption.3}{}} \newlabel{fig:schem_back_conn}{{iii}{6}{Layout of the DIN41612 Connectors on the Backplane\relax }{figure.caption.3}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.5.1}Termination resistors}{5}{subsubsection.2.5.1}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.5.1}Termination resistors}{6}{subsubsection.2.5.1}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {iv}{\ignorespaces Measurement at around 1MHz bus clock on MS1\relax }}{6}{figure.caption.4}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {iv}{\ignorespaces Measurement at around 1MHz bus clock on MS1\relax }}{7}{figure.caption.4}\protected@file@percent }
\newlabel{fig:reflex}{{iv}{6}{Measurement at around 1MHz bus clock on MS1\relax }{figure.caption.4}{}} \newlabel{fig:reflex}{{iv}{7}{Measurement at around 1MHz bus clock on MS1\relax }{figure.caption.4}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.6}Case}{6}{subsection.2.6}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {2.6}Case}{7}{subsection.2.6}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {v}{\ignorespaces The case with installed backplane\relax }}{7}{figure.caption.5}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {v}{\ignorespaces The case with installed backplane\relax }}{8}{figure.caption.5}\protected@file@percent }
\newlabel{fig:case}{{v}{7}{The case with installed backplane\relax }{figure.caption.5}{}} \newlabel{fig:case}{{v}{8}{The case with installed backplane\relax }{figure.caption.5}{}}
\abx@aux@cite{pc16550}
\abx@aux@segm{0}{0}{pc16550}
\abx@aux@cite{pc16550}
\abx@aux@segm{0}{0}{pc16550}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.7}Serial Console}{9}{subsection.2.7}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.7.1}16550 UART}{9}{subsubsection.2.7.1}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {vi}{\ignorespaces PC-16550D Pinout\cite {pc16550}\relax }}{9}{figure.caption.6}\protected@file@percent }
\newlabel{fig:16550_pinout}{{vi}{9}{PC-16550D Pinout\cite {pc16550}\relax }{figure.caption.6}{}}
\abx@aux@cite{max232}
\abx@aux@segm{0}{0}{max232}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.7.2}MAX-232}{10}{subsubsection.2.7.2}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.7.3}Schematics}{10}{subsubsection.2.7.3}\protected@file@percent }
\abx@aux@cite{pc16550} \abx@aux@cite{pc16550}
\abx@aux@segm{0}{0}{pc16550} \abx@aux@segm{0}{0}{pc16550}
\abx@aux@cite{pc16550} \abx@aux@cite{pc16550}
\abx@aux@segm{0}{0}{pc16550} \abx@aux@segm{0}{0}{pc16550}
\abx@aux@cite{max232} \abx@aux@cite{max232}
\abx@aux@segm{0}{0}{max232} \abx@aux@segm{0}{0}{max232}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.7}Serial Console}{8}{subsection.2.7}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {vii}{\ignorespaces The schematic of the UART Module\relax }}{11}{figure.caption.7}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.7.1}16550 UART}{8}{subsubsection.2.7.1}\protected@file@percent } \newlabel{fig:schem_uart}{{vii}{11}{The schematic of the UART Module\relax }{figure.caption.7}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {vi}{\ignorespaces PC-16550D Pinout\cite {pc16550}\relax }}{8}{figure.caption.6}\protected@file@percent } \@writefile{toc}{\contentsline {paragraph}{Element Description}{12}{figure.caption.7}\protected@file@percent }
\newlabel{fig:16550_pinout}{{vi}{8}{PC-16550D Pinout\cite {pc16550}\relax }{figure.caption.6}{}} \@writefile{lof}{\contentsline {figure}{\numberline {viii}{\ignorespaces Measurement of the 1.8432 MHz Output on J1\relax }}{12}{figure.caption.8}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.7.2}MAX-232}{9}{subsubsection.2.7.2}\protected@file@percent } \newlabel{fig:uartquartz}{{viii}{12}{Measurement of the 1.8432 MHz Output on J1\relax }{figure.caption.8}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.7.3}Schematics}{9}{subsubsection.2.7.3}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {ix}{\ignorespaces Measurement of a character transmission before and after MAX-232\relax }}{13}{figure.caption.9}\protected@file@percent }
\newlabel{fig:uart232}{{ix}{13}{Measurement of a character transmission before and after MAX-232\relax }{figure.caption.9}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {x}{\ignorespaces Pinout of the RJ-45 Plug; Src: \url {https://www.wti.com/}\relax }}{13}{figure.caption.10}\protected@file@percent }
\newlabel{fig:rs232rj45}{{x}{13}{Pinout of the RJ-45 Plug; Src: \url {https://www.wti.com/}\relax }{figure.caption.10}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.7.4}Demonstration Software}{14}{subsubsection.2.7.4}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xi}{\ignorespaces Measurement of a character echo\relax }}{14}{figure.caption.11}\protected@file@percent }
\newlabel{fig:232_echo}{{xi}{14}{Measurement of a character echo\relax }{figure.caption.11}{}}
\@writefile{toc}{\contentsline {paragraph}{Transmit code}{14}{figure.caption.11}\protected@file@percent }
\newlabel{lst:16550-general}{{I}{14}{Read and write routines for the 16550 UART}{lstlisting.1}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {I}Read and write routines for the 16550 UART}{14}{lstlisting.1}\protected@file@percent }
\abx@aux@cite{pc16550} \abx@aux@cite{pc16550}
\abx@aux@segm{0}{0}{pc16550} \abx@aux@segm{0}{0}{pc16550}
\abx@aux@cite{pc16550} \newlabel{lst:16550-transmit}{{II}{16}{16550 INIT routines and single char transmission}{lstlisting.2}{}}
\abx@aux@segm{0}{0}{pc16550} \@writefile{lol}{\contentsline {lstlisting}{\numberline {II}16550 INIT routines and single char transmission}{16}{lstlisting.2}\protected@file@percent }
\abx@aux@cite{max232} \@writefile{lof}{\contentsline {figure}{\numberline {xii}{\ignorespaces Transmission of character A via the 16550 UART\relax }}{17}{figure.caption.12}\protected@file@percent }
\abx@aux@segm{0}{0}{max232} \newlabel{fig:16550A}{{xii}{17}{Transmission of character A via the 16550 UART\relax }{figure.caption.12}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {vii}{\ignorespaces The schematic of the UART Module\relax }}{10}{figure.caption.7}\protected@file@percent } \@writefile{toc}{\contentsline {paragraph}{Echo code}{17}{figure.caption.12}\protected@file@percent }
\newlabel{fig:schem_uart}{{vii}{10}{The schematic of the UART Module\relax }{figure.caption.7}{}} \newlabel{lst:16550-echo}{{III}{18}{16550 character echo}{lstlisting.3}{}}
\@writefile{toc}{\contentsline {paragraph}{Element Description}{11}{figure.caption.7}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {III}16550 character echo}{18}{lstlisting.3}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {viii}{\ignorespaces Measurement of the 1.8432 MHz Output on J1\relax }}{11}{figure.caption.8}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {2.8}Audio Digital-Analog-Converter}{18}{subsection.2.8}\protected@file@percent }
\newlabel{fig:uartquartz}{{viii}{11}{Measurement of the 1.8432 MHz Output on J1\relax }{figure.caption.8}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {ix}{\ignorespaces Measurement of a character transmission before and after MAX-232\relax }}{12}{figure.caption.9}\protected@file@percent }
\newlabel{fig:uart232}{{ix}{12}{Measurement of a character transmission before and after MAX-232\relax }{figure.caption.9}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {x}{\ignorespaces Pinout of the RJ-45 Plug; Src: \url {https://www.wti.com/}\relax }}{12}{figure.caption.10}\protected@file@percent }
\newlabel{fig:rs232rj45}{{x}{12}{Pinout of the RJ-45 Plug; Src: \url {https://www.wti.com/}\relax }{figure.caption.10}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.7.4}Demonstration Software}{13}{subsubsection.2.7.4}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xi}{\ignorespaces Measurement of a character echo\relax }}{13}{figure.caption.11}\protected@file@percent }
\newlabel{fig:232_echo}{{xi}{13}{Measurement of a character echo\relax }{figure.caption.11}{}}
\@writefile{toc}{\contentsline {paragraph}{Transmit code}{13}{figure.caption.11}\protected@file@percent }
\newlabel{lst:16550-general}{{I}{13}{Read and write routines for the 16550 UART}{lstlisting.1}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {I}Read and write routines for the 16550 UART}{13}{lstlisting.1}\protected@file@percent }
\abx@aux@cite{pc16550}
\abx@aux@segm{0}{0}{pc16550}
\newlabel{lst:16550-transmit}{{II}{15}{16550 INIT routines and single char transmission}{lstlisting.2}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {II}16550 INIT routines and single char transmission}{15}{lstlisting.2}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xii}{\ignorespaces Transmission of character A via the 16550 UART\relax }}{16}{figure.caption.12}\protected@file@percent }
\newlabel{fig:16550A}{{xii}{16}{Transmission of character A via the 16550 UART\relax }{figure.caption.12}{}}
\@writefile{toc}{\contentsline {paragraph}{Echo code}{16}{figure.caption.12}\protected@file@percent }
\newlabel{lst:16550-echo}{{III}{16}{16550 character echo}{lstlisting.3}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {III}16550 character echo}{16}{lstlisting.3}\protected@file@percent }
\abx@aux@cite{tlc7528} \abx@aux@cite{tlc7528}
\abx@aux@segm{0}{0}{tlc7528} \abx@aux@segm{0}{0}{tlc7528}
\abx@aux@cite{tlc7528} \abx@aux@cite{tlc7528}
\abx@aux@segm{0}{0}{tlc7528} \abx@aux@segm{0}{0}{tlc7528}
\@writefile{toc}{\contentsline {subsection}{\numberline {2.8}Audio Digital-Analog-Converter}{17}{subsection.2.8}\protected@file@percent }
\abx@aux@cite{tlc7528} \abx@aux@cite{tlc7528}
\abx@aux@segm{0}{0}{tlc7528} \abx@aux@segm{0}{0}{tlc7528}
\abx@aux@cite{tlc7528} \abx@aux@cite{tlc7528}
@ -123,110 +122,110 @@
\abx@aux@segm{0}{0}{idt7201} \abx@aux@segm{0}{0}{idt7201}
\abx@aux@cite{idt7201} \abx@aux@cite{idt7201}
\abx@aux@segm{0}{0}{idt7201} \abx@aux@segm{0}{0}{idt7201}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.1}TLC 7528 Dual R2R Ladder DAC}{18}{subsubsection.2.8.1}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.1}TLC 7528 Dual R2R Ladder DAC}{19}{subsubsection.2.8.1}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xiii}{\ignorespaces TLC-7528 Pinout\cite {tlc7528}\relax }}{18}{figure.caption.13}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xiii}{\ignorespaces TLC-7528 Pinout\cite {tlc7528}\relax }}{19}{figure.caption.13}\protected@file@percent }
\newlabel{fig:tlc7528_pinout}{{xiii}{18}{TLC-7528 Pinout\cite {tlc7528}\relax }{figure.caption.13}{}} \newlabel{fig:tlc7528_pinout}{{xiii}{19}{TLC-7528 Pinout\cite {tlc7528}\relax }{figure.caption.13}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.2}IDT7201 CMOS FIFO Buffer}{18}{subsubsection.2.8.2}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.2}IDT7201 CMOS FIFO Buffer}{19}{subsubsection.2.8.2}\protected@file@percent }
\abx@aux@cite{tlc7528} \abx@aux@cite{tlc7528}
\abx@aux@segm{0}{0}{tlc7528} \abx@aux@segm{0}{0}{tlc7528}
\abx@aux@cite{tlc7528} \abx@aux@cite{tlc7528}
\abx@aux@segm{0}{0}{tlc7528} \abx@aux@segm{0}{0}{tlc7528}
\abx@aux@cite{tlc7528} \abx@aux@cite{tlc7528}
\abx@aux@segm{0}{0}{tlc7528} \abx@aux@segm{0}{0}{tlc7528}
\@writefile{lof}{\contentsline {figure}{\numberline {xiv}{\ignorespaces IDT-7201 Pinout\cite {idt7201}\relax }}{19}{figure.caption.14}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xiv}{\ignorespaces IDT-7201 Pinout\cite {idt7201}\relax }}{20}{figure.caption.14}\protected@file@percent }
\newlabel{fig:idt7201_pinout}{{xiv}{19}{IDT-7201 Pinout\cite {idt7201}\relax }{figure.caption.14}{}} \newlabel{fig:idt7201_pinout}{{xiv}{20}{IDT-7201 Pinout\cite {idt7201}\relax }{figure.caption.14}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.3}Theory verfication}{19}{subsubsection.2.8.3}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.3}Theory verfication}{20}{subsubsection.2.8.3}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xv}{\ignorespaces TLC-7528 in voltage modet\cite {tlc7528}\relax }}{20}{figure.caption.15}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xv}{\ignorespaces TLC-7528 in voltage modet\cite {tlc7528}\relax }}{21}{figure.caption.15}\protected@file@percent }
\newlabel{fig:tlc7528_volt}{{xv}{20}{TLC-7528 in voltage modet\cite {tlc7528}\relax }{figure.caption.15}{}} \newlabel{fig:tlc7528_volt}{{xv}{21}{TLC-7528 in voltage modet\cite {tlc7528}\relax }{figure.caption.15}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {xvi}{\ignorespaces Measurement of a generated SAW signal via the TLC7528\relax }}{20}{figure.caption.16}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xvi}{\ignorespaces Measurement of a generated SAW signal via the TLC7528\relax }}{21}{figure.caption.16}\protected@file@percent }
\newlabel{fig:tlc7528_saw_nonlin}{{xvi}{20}{Measurement of a generated SAW signal via the TLC7528\relax }{figure.caption.16}{}} \newlabel{fig:tlc7528_saw_nonlin}{{xvi}{21}{Measurement of a generated SAW signal via the TLC7528\relax }{figure.caption.16}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.4}Schematics}{20}{subsubsection.2.8.4}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.4}Schematics}{21}{subsubsection.2.8.4}\protected@file@percent }
\abx@aux@cite{74hc374} \abx@aux@cite{74hc374}
\abx@aux@segm{0}{0}{74hc374} \abx@aux@segm{0}{0}{74hc374}
\@writefile{lof}{\contentsline {figure}{\numberline {xvii}{\ignorespaces The schematic of the DAC Module\relax }}{21}{figure.caption.17}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xvii}{\ignorespaces The schematic of the DAC Module\relax }}{22}{figure.caption.17}\protected@file@percent }
\newlabel{fig:schem_dac}{{xvii}{21}{The schematic of the DAC Module\relax }{figure.caption.17}{}} \newlabel{fig:schem_dac}{{xvii}{22}{The schematic of the DAC Module\relax }{figure.caption.17}{}}
\abx@aux@cite{74hc00} \abx@aux@cite{74hc00}
\abx@aux@segm{0}{0}{74hc00} \abx@aux@segm{0}{0}{74hc00}
\abx@aux@cite{iec60908} \abx@aux@cite{iec60908}
\abx@aux@segm{0}{0}{iec60908} \abx@aux@segm{0}{0}{iec60908}
\abx@aux@cite{audiob} \abx@aux@cite{audiob}
\abx@aux@segm{0}{0}{audiob} \abx@aux@segm{0}{0}{audiob}
\@writefile{toc}{\contentsline {paragraph}{Element Description}{22}{figure.caption.17}\protected@file@percent } \@writefile{toc}{\contentsline {paragraph}{Element Description}{23}{figure.caption.17}\protected@file@percent }
\@writefile{toc}{\contentsline {paragraph}{NE55 Clock Source}{22}{figure.caption.17}\protected@file@percent } \@writefile{toc}{\contentsline {paragraph}{NE55 Clock Source}{24}{figure.caption.17}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.5}Demonstration Software}{23}{subsubsection.2.8.5}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {2.8.5}Demonstration Software}{24}{subsubsection.2.8.5}\protected@file@percent }
\@writefile{toc}{\contentsline {paragraph}{SAW Generator}{23}{subsubsection.2.8.5}\protected@file@percent } \@writefile{toc}{\contentsline {paragraph}{SAW Generator}{24}{subsubsection.2.8.5}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xviii}{\ignorespaces Measurement of a generated SAW signal with the FIFO Empty flag\relax }}{23}{figure.caption.18}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xviii}{\ignorespaces Measurement of a generated SAW signal with the FIFO Empty flag\relax }}{24}{figure.caption.18}\protected@file@percent }
\newlabel{fig:tlc7528_saw_fifo}{{xviii}{23}{Measurement of a generated SAW signal with the FIFO Empty flag\relax }{figure.caption.18}{}} \newlabel{fig:tlc7528_saw_fifo}{{xviii}{24}{Measurement of a generated SAW signal with the FIFO Empty flag\relax }{figure.caption.18}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {xix}{\ignorespaces A transmission between the FIFO and the DAC\relax }}{24}{figure.caption.19}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xix}{\ignorespaces A transmission between the FIFO and the DAC\relax }}{25}{figure.caption.19}\protected@file@percent }
\newlabel{fig:fifo_dac}{{xix}{24}{A transmission between the FIFO and the DAC\relax }{figure.caption.19}{}} \newlabel{fig:fifo_dac}{{xix}{25}{A transmission between the FIFO and the DAC\relax }{figure.caption.19}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {xx}{\ignorespaces A fifo store operation in contrast to the load operation\relax }}{24}{figure.caption.20}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xx}{\ignorespaces A fifo store operation in contrast to the load operation\relax }}{25}{figure.caption.20}\protected@file@percent }
\newlabel{fig:fifo_dac_store}{{xx}{24}{A fifo store operation in contrast to the load operation\relax }{figure.caption.20}{}} \newlabel{fig:fifo_dac_store}{{xx}{25}{A fifo store operation in contrast to the load operation\relax }{figure.caption.20}{}}
\newlabel{lst:dac_saw}{{IV}{24}{SAW Generation for the DAC with FIFO}{lstlisting.4}{}} \newlabel{lst:dac_saw}{{IV}{25}{SAW Generation for the DAC with FIFO}{lstlisting.4}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {IV}SAW Generation for the DAC with FIFO}{24}{lstlisting.4}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {IV}SAW Generation for the DAC with FIFO}{25}{lstlisting.4}\protected@file@percent }
\abx@aux@cite{atmega2560} \abx@aux@cite{atmega2560}
\abx@aux@segm{0}{0}{atmega2560} \abx@aux@segm{0}{0}{atmega2560}
\@writefile{toc}{\contentsline {paragraph}{Sine Generator}{25}{lstnumber.4.11}\protected@file@percent } \@writefile{toc}{\contentsline {paragraph}{Sine Generator}{26}{lstnumber.4.11}\protected@file@percent }
\newlabel{lst:dac_sine_lut}{{V}{25}{Sine LUT Generation}{lstlisting.5}{}} \newlabel{lst:dac_sine_lut}{{V}{26}{Sine LUT Generation}{lstlisting.5}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {V}Sine LUT Generation}{25}{lstlisting.5}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {V}Sine LUT Generation}{26}{lstlisting.5}\protected@file@percent }
\newlabel{lst:dac_sine}{{VI}{25}{DAC Sine Generation}{lstlisting.6}{}} \newlabel{lst:dac_sine}{{VI}{26}{DAC Sine Generation}{lstlisting.6}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {VI}DAC Sine Generation}{25}{lstlisting.6}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {VI}DAC Sine Generation}{26}{lstlisting.6}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xxi}{\ignorespaces Storage and retrieval of a sine to and from the FIFO\relax }}{26}{figure.caption.21}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xxi}{\ignorespaces Storage and retrieval of a sine to and from the FIFO\relax }}{27}{figure.caption.21}\protected@file@percent }
\newlabel{fig:fifo_sine_store}{{xxi}{26}{Storage and retrieval of a sine to and from the FIFO\relax }{figure.caption.21}{}} \newlabel{fig:fifo_sine_store}{{xxi}{27}{Storage and retrieval of a sine to and from the FIFO\relax }{figure.caption.21}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {xxii}{\ignorespaces Measuremet of the generated sine from the sine LUT on DACA and DACB\relax }}{26}{figure.caption.22}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xxii}{\ignorespaces Measuremet of the generated sine from the sine LUT on DACA and DACB\relax }}{27}{figure.caption.22}\protected@file@percent }
\newlabel{fig:sine_dacab}{{xxii}{26}{Measuremet of the generated sine from the sine LUT on DACA and DACB\relax }{figure.caption.22}{}} \newlabel{fig:sine_dacab}{{xxii}{27}{Measuremet of the generated sine from the sine LUT on DACA and DACB\relax }{figure.caption.22}{}}
\@writefile{toc}{\contentsline {section}{\numberline {3}Addressing DACA and DACB}{26}{section.3}\protected@file@percent }
\abx@aux@cite{lvlshift} \abx@aux@cite{lvlshift}
\abx@aux@segm{0}{0}{lvlshift} \abx@aux@segm{0}{0}{lvlshift}
\@writefile{toc}{\contentsline {subsection}{\numberline {3.1}FPGA to Hardware interface}{27}{subsection.3.1}\protected@file@percent } \@writefile{toc}{\contentsline {section}{\numberline {3}Addressing DACA and DACB}{28}{section.3}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xxiii}{\ignorespaces 3.3V to 5V conversion using the level shifter\relax }}{27}{figure.caption.23}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {3.1}FPGA to Hardware interface}{28}{subsection.3.1}\protected@file@percent }
\newlabel{fig:3v35v}{{xxiii}{27}{3.3V to 5V conversion using the level shifter\relax }{figure.caption.23}{}} \@writefile{lof}{\contentsline {figure}{\numberline {xxiii}{\ignorespaces 3.3V to 5V conversion using the level shifter\relax }}{29}{figure.caption.23}\protected@file@percent }
\newlabel{fig:3v35v}{{xxiii}{29}{3.3V to 5V conversion using the level shifter\relax }{figure.caption.23}{}}
\abx@aux@cite{lvlshift} \abx@aux@cite{lvlshift}
\abx@aux@segm{0}{0}{lvlshift} \abx@aux@segm{0}{0}{lvlshift}
\abx@aux@cite{lvlshift} \abx@aux@cite{lvlshift}
\abx@aux@segm{0}{0}{lvlshift} \abx@aux@segm{0}{0}{lvlshift}
\@writefile{lof}{\contentsline {figure}{\numberline {xxiv}{\ignorespaces 5V to 3.3V conversion using the level shifter\relax }}{28}{figure.caption.24}\protected@file@percent }
\newlabel{fig:5v3v3}{{xxiv}{28}{5V to 3.3V conversion using the level shifter\relax }{figure.caption.24}{}}
\abx@aux@cite{DB3S406F0L} \abx@aux@cite{DB3S406F0L}
\abx@aux@segm{0}{0}{DB3S406F0L} \abx@aux@segm{0}{0}{DB3S406F0L}
\@writefile{lof}{\contentsline {figure}{\numberline {xxiv}{\ignorespaces 5V to 3.3V conversion using the level shifter\relax }}{30}{figure.caption.24}\protected@file@percent }
\newlabel{fig:5v3v3}{{xxiv}{30}{5V to 3.3V conversion using the level shifter\relax }{figure.caption.24}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {xxv}{\ignorespaces The internal schematics of the level shifter\cite {lvlshift}\relax }}{30}{figure.caption.25}\protected@file@percent }
\newlabel{fig:schem_lvlshift}{{xxv}{30}{The internal schematics of the level shifter\cite {lvlshift}\relax }{figure.caption.25}{}}
\abx@aux@cite{ad2} \abx@aux@cite{ad2}
\abx@aux@segm{0}{0}{ad2} \abx@aux@segm{0}{0}{ad2}
\abx@aux@cite{ad2} \abx@aux@cite{ad2}
\abx@aux@segm{0}{0}{ad2} \abx@aux@segm{0}{0}{ad2}
\@writefile{lof}{\contentsline {figure}{\numberline {xxv}{\ignorespaces The internal schematics of the level shifter\cite {lvlshift}\relax }}{29}{figure.caption.25}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {3.1.1}Measurement error}{31}{subsubsection.3.1.1}\protected@file@percent }
\newlabel{fig:schem_lvlshift}{{xxv}{29}{The internal schematics of the level shifter\cite {lvlshift}\relax }{figure.caption.25}{}} \@writefile{lof}{\contentsline {figure}{\numberline {xxvi}{\ignorespaces The internal clamping diodes of the Analog Discovery 2\cite {ad2}\relax }}{31}{figure.caption.26}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {3.1.1}Measurement error}{29}{subsubsection.3.1.1}\protected@file@percent } \newlabel{fig:ad2_diode}{{xxvi}{31}{The internal clamping diodes of the Analog Discovery 2\cite {ad2}\relax }{figure.caption.26}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {xxvi}{\ignorespaces The internal clamping diodes of the Analog Discovery 2\cite {ad2}\relax }}{30}{figure.caption.26}\protected@file@percent } \@writefile{toc}{\contentsline {section}{\numberline {4}Textadventure}{31}{section.4}\protected@file@percent }
\newlabel{fig:ad2_diode}{{xxvi}{30}{The internal clamping diodes of the Analog Discovery 2\cite {ad2}\relax }{figure.caption.26}{}} \@writefile{toc}{\contentsline {subsection}{\numberline {4.1}General Implementation details}{32}{subsection.4.1}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {4}Textadventure}{30}{section.4}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1}General definitions and pinout of the AVR}{32}{subsubsection.4.1.1}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {4.1}General Implementation details}{30}{subsection.4.1}\protected@file@percent } \newlabel{lst:textadv-avr.h}{{VII}{33}{The avr.h header file}{lstlisting.7}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.1}General definitions and pinout of the AVR}{30}{subsubsection.4.1.1}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {VII}The avr.h header file}{33}{lstlisting.7}\protected@file@percent }
\newlabel{lst:textadv-avr.h}{{VII}{30}{The avr.h header file}{lstlisting.7}{}} \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.2}Read and Write routines}{34}{subsubsection.4.1.2}\protected@file@percent }
\@writefile{lol}{\contentsline {lstlisting}{\numberline {VII}The avr.h header file}{30}{lstlisting.7}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.3}UART and DAC update polling}{34}{subsubsection.4.1.3}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.2}Read and Write routines}{32}{subsubsection.4.1.2}\protected@file@percent } \newlabel{lst:textadv-routine}{{VIII}{34}{The routine function looped by the main}{lstlisting.8}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.1.3}UART and DAC update polling}{32}{subsubsection.4.1.3}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {VIII}The routine function looped by the main}{34}{lstlisting.8}\protected@file@percent }
\newlabel{lst:textadv-routine}{{VIII}{32}{The routine function looped by the main}{lstlisting.8}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {VIII}The routine function looped by the main}{32}{lstlisting.8}\protected@file@percent }
\newlabel{lst:textadv-routine-uart}{{IX}{32}{The routine function for the UART}{lstlisting.9}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {IX}The routine function for the UART}{32}{lstlisting.9}\protected@file@percent }
\abx@aux@cite{atmega2560} \abx@aux@cite{atmega2560}
\abx@aux@segm{0}{0}{atmega2560} \abx@aux@segm{0}{0}{atmega2560}
\newlabel{lst:textadv-routine-dac}{{X}{33}{The routine function for the DAC}{lstlisting.10}{}} \newlabel{lst:textadv-routine-uart}{{IX}{35}{The routine function for the UART}{lstlisting.9}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {X}The routine function for the DAC}{33}{lstlisting.10}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {IX}The routine function for the UART}{35}{lstlisting.9}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {4.2}DAC sound generation}{33}{subsection.4.2}\protected@file@percent } \newlabel{lst:textadv-routine-dac}{{X}{35}{The routine function for the DAC}{lstlisting.10}{}}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.1}DAC modes}{33}{subsubsection.4.2.1}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {X}The routine function for the DAC}{35}{lstlisting.10}\protected@file@percent }
\newlabel{lst:textadv-dac-modes}{{XI}{34}{The DAC operation modes}{lstlisting.11}{}} \@writefile{toc}{\contentsline {subsection}{\numberline {4.2}DAC sound generation}{35}{subsection.4.2}\protected@file@percent }
\@writefile{lol}{\contentsline {lstlisting}{\numberline {XI}The DAC operation modes}{34}{lstlisting.11}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.1}DAC modes}{35}{subsubsection.4.2.1}\protected@file@percent }
\newlabel{lst:textadv-dac-gen}{{XII}{34}{The DAC waveform generation code}{lstlisting.12}{}} \newlabel{lst:textadv-dac-modes}{{XI}{36}{The DAC operation modes}{lstlisting.11}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {XII}The DAC waveform generation code}{34}{lstlisting.12}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {XI}The DAC operation modes}{36}{lstlisting.11}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.2}Tones and Tracks}{37}{subsubsection.4.2.2}\protected@file@percent } \newlabel{lst:textadv-dac-gen}{{XII}{37}{The DAC waveform generation code}{lstlisting.12}{}}
\newlabel{lst:textadv-isr}{{XIII}{37}{The ISR which fires every millisecond}{lstlisting.13}{}} \@writefile{lol}{\contentsline {lstlisting}{\numberline {XII}The DAC waveform generation code}{37}{lstlisting.12}\protected@file@percent }
\@writefile{lol}{\contentsline {lstlisting}{\numberline {XIII}The ISR which fires every millisecond}{37}{lstlisting.13}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.2}Tones and Tracks}{40}{subsubsection.4.2.2}\protected@file@percent }
\newlabel{lst:textadv-upsnd}{{XIV}{38}{The sound update function}{lstlisting.14}{}} \newlabel{lst:textadv-isr}{{XIII}{40}{The ISR which fires every millisecond}{lstlisting.13}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {XIV}The sound update function}{38}{lstlisting.14}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {XIII}The ISR which fires every millisecond}{40}{lstlisting.13}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xxvii}{\ignorespaces The output of an example track part 1\relax }}{40}{figure.caption.27}\protected@file@percent } \newlabel{lst:textadv-upsnd}{{XIV}{40}{The sound update function}{lstlisting.14}{}}
\newlabel{fig:textadv_track_ex1}{{xxvii}{40}{The output of an example track part 1\relax }{figure.caption.27}{}} \@writefile{lol}{\contentsline {lstlisting}{\numberline {XIV}The sound update function}{40}{lstlisting.14}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xxviii}{\ignorespaces The output of an example track part 2\relax }}{41}{figure.caption.28}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xxvii}{\ignorespaces The output of an example track part 1\relax }}{42}{figure.caption.27}\protected@file@percent }
\newlabel{fig:textadv_track_ex2}{{xxviii}{41}{The output of an example track part 2\relax }{figure.caption.28}{}} \newlabel{fig:textadv_track_ex1}{{xxvii}{42}{The output of an example track part 1\relax }{figure.caption.27}{}}
\@writefile{lof}{\contentsline {figure}{\numberline {xxviii}{\ignorespaces The output of an example track part 2\relax }}{43}{figure.caption.28}\protected@file@percent }
\newlabel{fig:textadv_track_ex2}{{xxviii}{43}{The output of an example track part 2\relax }{figure.caption.28}{}}
\abx@aux@cite{dunnet} \abx@aux@cite{dunnet}
\abx@aux@segm{0}{0}{dunnet} \abx@aux@segm{0}{0}{dunnet}
\abx@aux@cite{ascii} \abx@aux@cite{ascii}
@ -237,49 +236,84 @@
\abx@aux@segm{0}{0}{ascii} \abx@aux@segm{0}{0}{ascii}
\abx@aux@cite{vt100} \abx@aux@cite{vt100}
\abx@aux@segm{0}{0}{vt100} \abx@aux@segm{0}{0}{vt100}
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.3}Track switching}{42}{subsubsection.4.2.3}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.2.3}Track switching}{44}{subsubsection.4.2.3}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {4.3}User command interpretation}{42}{subsection.4.3}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {4.3}User command interpretation}{44}{subsection.4.3}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.1}Command structure and parsing}{42}{subsubsection.4.3.1}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.1}Command structure and parsing}{44}{subsubsection.4.3.1}\protected@file@percent }
\newlabel{lst:textadv-ingest}{{XV}{42}{The character ingest function}{lstlisting.15}{}} \newlabel{lst:textadv-ingest}{{XV}{44}{The character ingest function}{lstlisting.15}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {XV}The character ingest function}{42}{lstlisting.15}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {XV}The character ingest function}{44}{lstlisting.15}\protected@file@percent }
\newlabel{lst:textadv-parsecmd}{{XVI}{43}{The command parsing function}{lstlisting.16}{}} \newlabel{lst:textadv-parsecmd}{{XVI}{45}{The command parsing function}{lstlisting.16}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {XVI}The command parsing function}{43}{lstlisting.16}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {XVI}The command parsing function}{45}{lstlisting.16}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.2}Command parameters}{43}{subsubsection.4.3.2}\protected@file@percent } \@writefile{toc}{\contentsline {subsubsection}{\numberline {4.3.2}Command parameters}{46}{subsubsection.4.3.2}\protected@file@percent }
\newlabel{lst:textadv-perfact}{{XVII}{44}{The command execution routine}{lstlisting.17}{}} \newlabel{lst:textadv-perfact}{{XVII}{46}{The command execution routine}{lstlisting.17}{}}
\@writefile{lol}{\contentsline {lstlisting}{\numberline {XVII}The command execution routine}{44}{lstlisting.17}\protected@file@percent } \@writefile{lol}{\contentsline {lstlisting}{\numberline {XVII}The command execution routine}{46}{lstlisting.17}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {4.4}Gameplay}{45}{subsection.4.4}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {4.4}Gameplay}{47}{subsection.4.4}\protected@file@percent }
\abx@aux@cite{atmega2560} \abx@aux@cite{atmega2560}
\abx@aux@segm{0}{0}{atmega2560} \abx@aux@segm{0}{0}{atmega2560}
\abx@aux@cite{elf} \abx@aux@cite{elf}
\abx@aux@segm{0}{0}{elf} \abx@aux@segm{0}{0}{elf}
\abx@aux@cite{progmem} \abx@aux@cite{progmem}
\abx@aux@segm{0}{0}{progmem} \abx@aux@segm{0}{0}{progmem}
\@writefile{lof}{\contentsline {figure}{\numberline {xxix}{\ignorespaces A regular beginning of the game\relax }}{46}{figure.caption.29}\protected@file@percent } \@writefile{lof}{\contentsline {figure}{\numberline {xxix}{\ignorespaces A regular beginning of the game\relax }}{48}{figure.caption.29}\protected@file@percent }
\newlabel{fig:tetadv_gameplay}{{xxix}{46}{A regular beginning of the game\relax }{figure.caption.29}{}} \newlabel{fig:tetadv_gameplay}{{xxix}{48}{A regular beginning of the game\relax }{figure.caption.29}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {4.5}Memory constraints}{46}{subsection.4.5}\protected@file@percent } \@writefile{toc}{\contentsline {subsection}{\numberline {4.5}Memory constraints}{49}{subsection.4.5}\protected@file@percent }
\babel@aux{ngerman}{} \abx@aux@cite{ghdl}
\@writefile{toc}{\contentsline {section}{\numberline {5}Erkl"arung der Eigenst"andigkeit der Arbeit}{48}{section.5}\protected@file@percent } \abx@aux@segm{0}{0}{ghdl}
\HyPL@Entry{54<</S/R>>} \abx@aux@cite{gtkwave}
\babel@aux{english}{} \abx@aux@segm{0}{0}{gtkwave}
\@writefile{toc}{\contentsline {section}{\numberline {I\tmspace +\thickmuskip {.2777em}}List of Figures}{I}{section.1}\protected@file@percent } \abx@aux@cite{yosys}
\@writefile{toc}{\contentsline {section}{\numberline {II\tmspace +\thickmuskip {.2777em}}List of Tables}{I}{section.2}\protected@file@percent } \abx@aux@segm{0}{0}{yosys}
\@writefile{toc}{\contentsline {section}{\numberline {III\tmspace +\thickmuskip {.2777em}}Listings}{I}{section.3}\protected@file@percent } \abx@aux@cite{yosys}
\@writefile{toc}{\contentsline {section}{Anhang}{IV}{section.3}\protected@file@percent } \abx@aux@segm{0}{0}{yosys}
\abx@aux@refcontextdefaultsdone \abx@aux@cite{nextpnr-xilinx}
\abx@aux@defaultrefcontext{0}{ad2}{none/global//global/global} \abx@aux@segm{0}{0}{nextpnr-xilinx}
\abx@aux@defaultrefcontext{0}{atmega2560}{none/global//global/global} \abx@aux@cite{prjxray}
\abx@aux@defaultrefcontext{0}{pc16550}{none/global//global/global} \abx@aux@segm{0}{0}{prjxray}
\abx@aux@defaultrefcontext{0}{max232}{none/global//global/global} \abx@aux@cite{open-fpga-loader}
\abx@aux@defaultrefcontext{0}{tlc7528}{none/global//global/global} \abx@aux@segm{0}{0}{open-fpga-loader}
\abx@aux@defaultrefcontext{0}{idt7201}{none/global//global/global} \@writefile{toc}{\contentsline {part}{I\hspace {1em}A short introduction to VHDL}{50}{part.1}\protected@file@percent }
\abx@aux@defaultrefcontext{0}{74hc374}{none/global//global/global} \@writefile{toc}{\contentsline {section}{\numberline {5}Prerequisites}{50}{section.5}\protected@file@percent }
\abx@aux@defaultrefcontext{0}{74hc00}{none/global//global/global} \@writefile{toc}{\contentsline {section}{\numberline {6}Creating a design}{50}{section.6}\protected@file@percent }
\abx@aux@defaultrefcontext{0}{iec60908}{none/global//global/global} \@writefile{toc}{\contentsline {section}{\numberline {7}Simulating a design}{52}{section.7}\protected@file@percent }
\abx@aux@defaultrefcontext{0}{audiob}{none/global//global/global} \@writefile{lof}{\contentsline {figure}{\numberline {xxx}{\ignorespaces Screenshot of the resulting waveform in GTKWave\relax }}{53}{figure.caption.30}\protected@file@percent }
\abx@aux@defaultrefcontext{0}{lvlshift}{none/global//global/global} \@writefile{toc}{\contentsline {section}{\numberline {8}Synthesizing a design}{53}{section.8}\protected@file@percent }
\abx@aux@defaultrefcontext{0}{DB3S406F0L}{none/global//global/global} \abx@aux@cite{nandgame}
\abx@aux@defaultrefcontext{0}{dunnet}{none/global//global/global} \abx@aux@segm{0}{0}{nandgame}
\abx@aux@defaultrefcontext{0}{ascii}{none/global//global/global} \abx@aux@cite{breadboard_computer}
\abx@aux@defaultrefcontext{0}{vt100}{none/global//global/global} \abx@aux@segm{0}{0}{breadboard_computer}
\abx@aux@defaultrefcontext{0}{elf}{none/global//global/global} \@writefile{toc}{\contentsline {part}{II\hspace {1em}Meta}{54}{part.2}\protected@file@percent }
\abx@aux@defaultrefcontext{0}{progmem}{none/global//global/global} \@writefile{toc}{\contentsline {section}{\numberline {9}History}{54}{section.9}\protected@file@percent }
\abx@aux@cite{yosys-paper}
\abx@aux@segm{0}{0}{yosys-paper}
\abx@aux@cite{yosys}
\abx@aux@segm{0}{0}{yosys}
\abx@aux@cite{nextpnr}
\abx@aux@segm{0}{0}{nextpnr}
\abx@aux@cite{ghdlsynth-beta}
\abx@aux@segm{0}{0}{ghdlsynth-beta}
\abx@aux@cite{ghdl}
\abx@aux@segm{0}{0}{ghdl}
\abx@aux@cite{nextpnr-xilinx}
\abx@aux@segm{0}{0}{nextpnr-xilinx}
\abx@aux@cite{prjxray}
\abx@aux@segm{0}{0}{prjxray}
\@writefile{toc}{\contentsline {section}{\numberline {10}Tooling}{56}{section.10}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {10.1}Vendor Tools}{56}{subsection.10.1}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {10.2}Free Software Tools}{56}{subsection.10.2}\protected@file@percent }
\@writefile{toc}{\contentsline {section}{\numberline {11}Peripherals}{57}{section.11}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {11.1}UART}{57}{subsection.11.1}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {11.2}DVI graphics}{57}{subsection.11.2}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {11.2.1}VGA timing}{57}{subsubsection.11.2.1}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xxxi}{\ignorespaces Block diagram of the video core\relax }}{58}{figure.caption.31}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {11.2.2}Text renderer}{58}{subsubsection.11.2.2}\protected@file@percent }
\abx@aux@cite{liteeth}
\abx@aux@segm{0}{0}{liteeth}
\@writefile{lof}{\contentsline {figure}{\numberline {xxxii}{\ignorespaces Diagram of VGA timing intervals\relax }}{59}{figure.caption.32}\protected@file@percent }
\@writefile{toc}{\contentsline {subsubsection}{\numberline {11.2.3}TMDS encoder}{59}{subsubsection.11.2.3}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {11.3}Ethernet}{59}{subsection.11.3}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xxxiii}{\ignorespaces Block diagram of the text renderer\relax }}{60}{figure.caption.33}\protected@file@percent }
\@writefile{toc}{\contentsline {subsection}{\numberline {11.4}WS2812 driver}{60}{subsection.11.4}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xxxiv}{\ignorespaces Block diagram of the WS2812 driver\relax }}{60}{figure.caption.34}\protected@file@percent }
\@writefile{lof}{\contentsline {figure}{\numberline {xxxv}{\ignorespaces Timing diagram for the WS2812 serial protocol\relax }}{61}{figure.caption.35}\protected@file@percent }
\newlabel{fig:ws2812_timing}{{xxxv}{61}{Timing diagram for the WS2812 serial protocol\relax }{figure.caption.35}{}}
\@writefile{toc}{\contentsline {subsection}{\numberline {11.5}DRAM}{61}{subsection.11.5}\protected@file@percent }
\@writefile{toc}{\contentsline {part}{III\hspace {1em}The Core}{61}{part.3}\protected@file@percent }

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main.bcf
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@ -2168,21 +2168,20 @@
<bcf:citekey order="37">atmega2560</bcf:citekey> <bcf:citekey order="37">atmega2560</bcf:citekey>
<bcf:citekey order="38">elf</bcf:citekey> <bcf:citekey order="38">elf</bcf:citekey>
<bcf:citekey order="39">progmem</bcf:citekey> <bcf:citekey order="39">progmem</bcf:citekey>
</bcf:section> <bcf:citekey order="40">ghdl</bcf:citekey>
<!-- SORTING TEMPLATES --> <bcf:citekey order="41">gtkwave</bcf:citekey>
<bcf:sortingtemplate name="none"> <bcf:citekey order="42">yosys</bcf:citekey>
<bcf:sort order="1"> <bcf:citekey order="43">yosys</bcf:citekey>
<bcf:sortitem order="1">citeorder</bcf:sortitem> <bcf:citekey order="44">nextpnr-xilinx</bcf:citekey>
</bcf:sort> <bcf:citekey order="45">prjxray</bcf:citekey>
</bcf:sortingtemplate> <bcf:citekey order="46">open-fpga-loader</bcf:citekey>
<!-- DATALISTS --> <bcf:citekey order="47">nandgame</bcf:citekey>
<bcf:datalist section="0" <bcf:citekey order="48">breadboard_computer</bcf:citekey>
name="none/global//global/global" <bcf:citekey order="49">yosys-paper</bcf:citekey>
type="entry" <bcf:citekey order="49">yosys</bcf:citekey>
sortingtemplatename="none" <bcf:citekey order="50">nextpnr</bcf:citekey>
sortingnamekeytemplatename="global" <bcf:citekey order="51">ghdlsynth-beta</bcf:citekey>
labelprefix="" <bcf:citekey order="52">ghdl</bcf:citekey>
uniquenametemplatename="global" <bcf:citekey order="53">nextpnr-xilinx</bcf:citekey>
labelalphanametemplatename="global"> <bcf:citekey order="54">prjxray</bcf:citekey>
</bcf:datalist> <bcf:citekey order="55">liteeth</bcf:citekey>
</bcf:controlfile>

2243
main.log
View file

File diff suppressed because it is too large Load diff

25
main.out
View file

@ -46,8 +46,23 @@
\BOOKMARK [3][-]{subsubsection.4.3.2}{\376\377\000C\000o\000m\000m\000a\000n\000d\000\040\000p\000a\000r\000a\000m\000e\000t\000e\000r\000s}{subsection.4.3}% 46 \BOOKMARK [3][-]{subsubsection.4.3.2}{\376\377\000C\000o\000m\000m\000a\000n\000d\000\040\000p\000a\000r\000a\000m\000e\000t\000e\000r\000s}{subsection.4.3}% 46
\BOOKMARK [2][-]{subsection.4.4}{\376\377\000G\000a\000m\000e\000p\000l\000a\000y}{section.4}% 47 \BOOKMARK [2][-]{subsection.4.4}{\376\377\000G\000a\000m\000e\000p\000l\000a\000y}{section.4}% 47
\BOOKMARK [2][-]{subsection.4.5}{\376\377\000M\000e\000m\000o\000r\000y\000\040\000c\000o\000n\000s\000t\000r\000a\000i\000n\000t\000s}{section.4}% 48 \BOOKMARK [2][-]{subsection.4.5}{\376\377\000M\000e\000m\000o\000r\000y\000\040\000c\000o\000n\000s\000t\000r\000a\000i\000n\000t\000s}{section.4}% 48
\BOOKMARK [1][-]{section.5}{\376\377\000E\000r\000k\000l\000\344\000r\000u\000n\000g\000\040\000d\000e\000r\000\040\000E\000i\000g\000e\000n\000s\000t\000\344\000n\000d\000i\000g\000k\000e\000i\000t\000\040\000d\000e\000r\000\040\000A\000r\000b\000e\000i\000t}{}% 49 \BOOKMARK [0][-]{part.1}{\376\377\000I\000\040\000A\000\040\000s\000h\000o\000r\000t\000\040\000i\000n\000t\000r\000o\000d\000u\000c\000t\000i\000o\000n\000\040\000t\000o\000\040\000V\000H\000D\000L}{}% 49
\BOOKMARK [1][-]{section.1}{\376\377\000L\000i\000s\000t\000\040\000o\000f\000\040\000F\000i\000g\000u\000r\000e\000s}{}% 50 \BOOKMARK [1][-]{section.5}{\376\377\000P\000r\000e\000r\000e\000q\000u\000i\000s\000i\000t\000e\000s}{part.1}% 50
\BOOKMARK [1][-]{section.2}{\376\377\000L\000i\000s\000t\000\040\000o\000f\000\040\000T\000a\000b\000l\000e\000s}{}% 51 \BOOKMARK [1][-]{section.6}{\376\377\000C\000r\000e\000a\000t\000i\000n\000g\000\040\000a\000\040\000d\000e\000s\000i\000g\000n}{part.1}% 51
\BOOKMARK [1][-]{section.3}{\376\377\000L\000i\000s\000t\000i\000n\000g\000s}{}% 52 \BOOKMARK [1][-]{section.7}{\376\377\000S\000i\000m\000u\000l\000a\000t\000i\000n\000g\000\040\000a\000\040\000d\000e\000s\000i\000g\000n}{part.1}% 52
\BOOKMARK [1][-]{section.3}{\376\377\000A\000n\000h\000a\000n\000g}{}% 53 \BOOKMARK [1][-]{section.8}{\376\377\000S\000y\000n\000t\000h\000e\000s\000i\000z\000i\000n\000g\000\040\000a\000\040\000d\000e\000s\000i\000g\000n}{part.1}% 53
\BOOKMARK [0][-]{part.2}{\376\377\000I\000I\000\040\000M\000e\000t\000a}{}% 54
\BOOKMARK [1][-]{section.9}{\376\377\000H\000i\000s\000t\000o\000r\000y}{part.2}% 55
\BOOKMARK [1][-]{section.10}{\376\377\000T\000o\000o\000l\000i\000n\000g}{part.2}% 56
\BOOKMARK [2][-]{subsection.10.1}{\376\377\000V\000e\000n\000d\000o\000r\000\040\000T\000o\000o\000l\000s}{section.10}% 57
\BOOKMARK [2][-]{subsection.10.2}{\376\377\000F\000r\000e\000e\000\040\000S\000o\000f\000t\000w\000a\000r\000e\000\040\000T\000o\000o\000l\000s}{section.10}% 58
\BOOKMARK [1][-]{section.11}{\376\377\000P\000e\000r\000i\000p\000h\000e\000r\000a\000l\000s}{part.2}% 59
\BOOKMARK [2][-]{subsection.11.1}{\376\377\000U\000A\000R\000T}{section.11}% 60
\BOOKMARK [2][-]{subsection.11.2}{\376\377\000D\000V\000I\000\040\000g\000r\000a\000p\000h\000i\000c\000s}{section.11}% 61
\BOOKMARK [3][-]{subsubsection.11.2.1}{\376\377\000V\000G\000A\000\040\000t\000i\000m\000i\000n\000g}{subsection.11.2}% 62
\BOOKMARK [3][-]{subsubsection.11.2.2}{\376\377\000T\000e\000x\000t\000\040\000r\000e\000n\000d\000e\000r\000e\000r}{subsection.11.2}% 63
\BOOKMARK [3][-]{subsubsection.11.2.3}{\376\377\000T\000M\000D\000S\000\040\000e\000n\000c\000o\000d\000e\000r}{subsection.11.2}% 64
\BOOKMARK [2][-]{subsection.11.3}{\376\377\000E\000t\000h\000e\000r\000n\000e\000t}{section.11}% 65
\BOOKMARK [2][-]{subsection.11.4}{\376\377\000W\000S\0002\0008\0001\0002\000\040\000d\000r\000i\000v\000e\000r}{section.11}% 66
\BOOKMARK [2][-]{subsection.11.5}{\376\377\000D\000R\000A\000M}{section.11}% 67
\BOOKMARK [0][-]{part.3}{\376\377\000I\000I\000I\000\040\000T\000h\000e\000\040\000C\000o\000r\000e}{}% 68

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main.pdf (Stored with Git LFS)
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main.tex
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@ -138,11 +138,10 @@ interpreted as gender neutral.
\DP\input{sections/DP/fpga_interface/main.tex} \DP\input{sections/DP/fpga_interface/main.tex}
\DP\input{sections/DP/textadv/main.tex} \DP\input{sections/DP/textadv/main.tex}
\clearpage \clearpage
%\MR\input{sections/Kapitel/MR/EntwicklungAufgaben.tex}
\subfile{sections/vhdl_intro/vhdl_intro.tex} \AB\subfile{sections/vhdl_intro/vhdl_intro.tex}
\subfile{sections/soc/soc.tex} \AB\subfile{sections/soc/soc.tex}
\subfile{sections/core/core.tex} \AB\subfile{sections/core/core.tex}
%==================================================================================== %====================================================================================
\allAuth \allAuth

69
main.toc
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@ -1,69 +0,0 @@
\babel@toc {english}{}
\boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax
\babel@toc {ngerman}{}
\babel@toc {ngerman}{}
\contentsline {section}{Gendererklärung}{i}{Doc-Start}%
\contentsline {section}{Kurzfassung/Abstract}{ii}{Doc-Start}%
\babel@toc {ngerman}{}
\babel@toc {ngerman}{}
\contentsline {section}{Result}{iii}{Doc-Start}%
\babel@toc {english}{}
\contentsline {section}{\numberline {1}Task description}{1}{section.1}%
\contentsline {subsection}{\numberline {1.1}Hardware}{1}{subsection.1.1}%
\contentsline {section}{\numberline {2}Hardware peripherials}{2}{section.2}%
\contentsline {subsection}{\numberline {2.1}Parallel bus}{2}{subsection.2.1}%
\contentsline {subsubsection}{\numberline {2.1.1}Address Bus}{2}{subsubsection.2.1.1}%
\contentsline {subsection}{\numberline {2.2}Data Bus}{3}{subsection.2.2}%
\contentsline {subsection}{\numberline {2.3}Control Bus}{3}{subsection.2.3}%
\contentsline {subsubsection}{\numberline {2.3.1}Master Reset}{3}{subsubsection.2.3.1}%
\contentsline {subsubsection}{\numberline {2.3.2}Write Not}{3}{subsubsection.2.3.2}%
\contentsline {subsubsection}{\numberline {2.3.3}Read Not}{3}{subsubsection.2.3.3}%
\contentsline {subsubsection}{\numberline {2.3.4}Module Select 1 and 2 Not}{3}{subsubsection.2.3.4}%
\contentsline {subsection}{\numberline {2.4}Testing and Measurement}{4}{subsection.2.4}%
\contentsline {subsubsection}{\numberline {2.4.1}Measurements}{4}{subsubsection.2.4.1}%
\contentsline {subsubsection}{\numberline {2.4.2}Testing}{4}{subsubsection.2.4.2}%
\contentsline {subsection}{\numberline {2.5}Backplane}{5}{subsection.2.5}%
\contentsline {subsubsection}{\numberline {2.5.1}Termination resistors}{5}{subsubsection.2.5.1}%
\contentsline {subsection}{\numberline {2.6}Case}{6}{subsection.2.6}%
\contentsline {subsection}{\numberline {2.7}Serial Console}{8}{subsection.2.7}%
\contentsline {subsubsection}{\numberline {2.7.1}16550 UART}{8}{subsubsection.2.7.1}%
\contentsline {subsubsection}{\numberline {2.7.2}MAX-232}{9}{subsubsection.2.7.2}%
\contentsline {subsubsection}{\numberline {2.7.3}Schematics}{9}{subsubsection.2.7.3}%
\contentsline {paragraph}{Element Description}{11}{figure.caption.7}%
\contentsline {subsubsection}{\numberline {2.7.4}Demonstration Software}{13}{subsubsection.2.7.4}%
\contentsline {paragraph}{Transmit code}{13}{figure.caption.11}%
\contentsline {paragraph}{Echo code}{16}{figure.caption.12}%
\contentsline {subsection}{\numberline {2.8}Audio Digital-Analog-Converter}{17}{subsection.2.8}%
\contentsline {subsubsection}{\numberline {2.8.1}TLC 7528 Dual R2R Ladder DAC}{18}{subsubsection.2.8.1}%
\contentsline {subsubsection}{\numberline {2.8.2}IDT7201 CMOS FIFO Buffer}{18}{subsubsection.2.8.2}%
\contentsline {subsubsection}{\numberline {2.8.3}Theory verfication}{19}{subsubsection.2.8.3}%
\contentsline {subsubsection}{\numberline {2.8.4}Schematics}{20}{subsubsection.2.8.4}%
\contentsline {paragraph}{Element Description}{22}{figure.caption.17}%
\contentsline {paragraph}{NE55 Clock Source}{22}{figure.caption.17}%
\contentsline {subsubsection}{\numberline {2.8.5}Demonstration Software}{23}{subsubsection.2.8.5}%
\contentsline {paragraph}{SAW Generator}{23}{subsubsection.2.8.5}%
\contentsline {paragraph}{Sine Generator}{25}{lstnumber.4.11}%
\contentsline {section}{\numberline {3}Addressing DACA and DACB}{26}{section.3}%
\contentsline {subsection}{\numberline {3.1}FPGA to Hardware interface}{27}{subsection.3.1}%
\contentsline {subsubsection}{\numberline {3.1.1}Measurement error}{29}{subsubsection.3.1.1}%
\contentsline {section}{\numberline {4}Textadventure}{30}{section.4}%
\contentsline {subsection}{\numberline {4.1}General Implementation details}{30}{subsection.4.1}%
\contentsline {subsubsection}{\numberline {4.1.1}General definitions and pinout of the AVR}{30}{subsubsection.4.1.1}%
\contentsline {subsubsection}{\numberline {4.1.2}Read and Write routines}{32}{subsubsection.4.1.2}%
\contentsline {subsubsection}{\numberline {4.1.3}UART and DAC update polling}{32}{subsubsection.4.1.3}%
\contentsline {subsection}{\numberline {4.2}DAC sound generation}{33}{subsection.4.2}%
\contentsline {subsubsection}{\numberline {4.2.1}DAC modes}{33}{subsubsection.4.2.1}%
\contentsline {subsubsection}{\numberline {4.2.2}Tones and Tracks}{37}{subsubsection.4.2.2}%
\contentsline {subsubsection}{\numberline {4.2.3}Track switching}{42}{subsubsection.4.2.3}%
\contentsline {subsection}{\numberline {4.3}User command interpretation}{42}{subsection.4.3}%
\contentsline {subsubsection}{\numberline {4.3.1}Command structure and parsing}{42}{subsubsection.4.3.1}%
\contentsline {subsubsection}{\numberline {4.3.2}Command parameters}{43}{subsubsection.4.3.2}%
\contentsline {subsection}{\numberline {4.4}Gameplay}{45}{subsection.4.4}%
\contentsline {subsection}{\numberline {4.5}Memory constraints}{46}{subsection.4.5}%
\babel@toc {ngerman}{}
\contentsline {section}{\numberline {5}Erkl"arung der Eigenst"andigkeit der Arbeit}{48}{section.5}%
\babel@toc {english}{}
\contentsline {section}{\numberline {I\tmspace +\thickmuskip {.2777em}}List of Figures}{I}{section.1}%
\contentsline {section}{\numberline {II\tmspace +\thickmuskip {.2777em}}List of Tables}{I}{section.2}%
\contentsline {section}{\numberline {III\tmspace +\thickmuskip {.2777em}}Listings}{I}{section.3}%
\contentsline {section}{Anhang}{IV}{section.3}%

2
preamble.tex
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@ -149,7 +149,7 @@
\makeindex \makeindex
%%% BibLaTeX settings %%% BibLaTeX settings
\usepackage[citestyle = ieee]{biblatex} \usepackage[style = verbose, dashed=false, citestyle = ieee]{biblatex}
\usepackage{csquotes} \usepackage{csquotes}
\addbibresource{./bibliographies/DP.bib} \addbibresource{./bibliographies/DP.bib}
\DeclareNameAlias{sortname}{family-given} \DeclareNameAlias{sortname}{family-given}

2
sections/DP/textadv/main.tex
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@ -13,7 +13,7 @@ Like the before examples, the textadventure was implemented on an ATMega2560
and uses 3 different Registers for transmission: PORTF, PORTK and PORTL for and uses 3 different Registers for transmission: PORTF, PORTK and PORTL for
address bus, data bus and control bus respectively, as can be seen in listing address bus, data bus and control bus respectively, as can be seen in listing
\ref{lst:textadv-avr.h} \ref{lst:textadv-avr.h}
\newpage
\lstinputlisting[language=C,frame=trBL, \lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage, breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-avr.h}, caption={The avr.h header file}, label={lst:textadv-avr.h}, caption={The avr.h header file},

18
sections/core/entities/alu_entity.vhd Normal file
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@ -0,0 +1,18 @@
entity alu is
port (
clk : in std_logic;
enable_math : in std_logic;
valid : out std_logic;
operation : in alu_operation_t;
a, b : in yarm_word;
math_result : out yarm_word;
-- compare inputs
-- do signed comparisons
enable_cmp : in std_logic;
cmp_signed : in std_logic;
cmp1, cmp2 : in yarm_word;
cmp_result : out compare_result_t
);
end alu;

54
sections/core/entities/control_entity.vhd Normal file
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@ -0,0 +1,54 @@
entity control is
generic (
RESET_VECTOR : yarm_word
);
port (
clk : in std_logic;
reset : in std_logic;
fetch_enable : out std_logic;
fetch_ready : in std_logic;
fetch_instr_out : in yarm_word;
decoder_enable : out std_logic;
decoder_instr_info_out : in instruction_info_t;
registers_data_a : in yarm_word;
registers_data_b : in yarm_word;
alu_enable_math : out std_logic;
alu_math_result : in yarm_word;
alu_valid : in std_logic;
alu_enable_cmp : out std_logic;
alu_cmp_result : in compare_result_t;
csr_enable : out std_logic;
csr_ready : in std_logic;
csr_data_read : in yarm_word;
csr_increase_instret : out std_logic;
datamem_enable : out std_logic;
datamem_ready : in std_logic;
alignment_raise_exc : out std_logic;
alignment_exc_data : out exception_data_t;
registers_read_enable : out std_logic;
registers_write_enable : out std_logic;
-- TRAP CONTROL
may_interrupt : out std_logic;
-- the stage that will receive an interrupt exception
interrupted_stage : out pipeline_stage_t;
do_trap : in std_logic;
trap_vector : in yarm_word;
trap_return_vec : in yarm_word;
return_trap : out std_logic;
-- instruction info records used as input for the respective stages
stage_inputs : out pipeline_frames_t
);
end control;

23
sections/core/entities/core_entity.vhd Normal file
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@ -0,0 +1,23 @@
entity core is
generic (
HART_ID : natural;
RESET_VECTOR : yarm_word := (others => '0')
);
port (
clk : in std_logic;
reset : in std_logic;
-- little-endian memory interface, 4 byte address alignment
MEM_addr : out yarm_word;
MEM_read : out std_logic;
MEM_write : out std_logic;
MEM_ready : in std_logic;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word;
external_int : in std_logic;
timer_int : in std_logic;
software_int : in std_logic
);
end core;

36
sections/core/entities/csr_entity.vhd Normal file
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@ -0,0 +1,36 @@
entity csr is
generic (
HART_ID : integer
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
ready : out std_logic;
instr_info_in : in instruction_info_t;
data_write : in yarm_word;
data_read : out yarm_word;
increase_instret : in std_logic;
external_int : in std_logic;
timer_int : in std_logic;
software_int : in std_logic;
interrupts_pending : out yarm_word;
interrupts_enabled : out yarm_word;
global_int_enabled : out std_logic;
mtvec_out : out yarm_word;
mepc_out : out yarm_word;
do_trap : in std_logic;
return_m_trap : in std_logic;
mepc_in : in yarm_word;
mcause_in : in yarm_trap_cause;
mtval_in : in yarm_word;
raise_exc : out std_logic;
exc_data : out exception_data_t
);
end csr;

21
sections/core/entities/decoder_entity.vhd Normal file
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@ -0,0 +1,21 @@
entity decoder is
port (
clk : in std_logic;
enable : in std_logic;
async_addr_rs1 : out register_addr_t;
async_addr_rs2 : out register_addr_t;
alu_muxsel_a : out mux_selector_t;
alu_muxsel_b : out mux_selector_t;
alu_muxsel_cmp2 : out mux_selector_t;
csr_muxsel_in : out mux_selector_t;
instr_info_in : in instruction_info_t;
instr_info_out : out instruction_info_t;
raise_exc : out std_logic;
exc_data : out exception_data_t
);
end decoder;

36
sections/core/entities/exception_control_entity.vhd Normal file
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@ -0,0 +1,36 @@
entity exception_control is
port (
clk : in std_logic;
fetch_raise_exc : in std_logic;
fetch_exc_data : in exception_data_t;
-- synchronous exceptions
decoder_raise_exc : in std_logic;
decoder_exc_data : in exception_data_t;
csr_raise_exc : in std_logic;
csr_exc_data : in exception_data_t;
alignment_raise_exc : in std_logic;
alignment_exc_data : in exception_data_t;
datamem_raise_exc : in std_logic;
datamem_exc_data : in exception_data_t;
-- interrupts
global_int_enabled : in std_logic;
interrupts_enabled : in yarm_word;
interrupts_pending : in yarm_word;
-- stage inputs for return address + trap value (instruction)
stage_inputs : in pipeline_frames_t;
interrupted_stage : in pipeline_stage_t;
may_interrupt : in std_logic;
do_trap : out std_logic;
trap_cause : out yarm_trap_cause;
trap_address : out yarm_word;
trap_value : out yarm_word
);
end exception_control;

16
sections/core/entities/memctl_entity.vhd Normal file
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@ -0,0 +1,16 @@
entity memctl is
port (
addr : in yarm_word;
-- data width
data_width : in datum_width_t;
-- perfom sign extension when reading short data
sign_extend : in std_logic;
data_read : out yarm_word;
data_write : in yarm_word;
MEM_addr : out yarm_word;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word
);
end memctl;

31
sections/core/entities/memory_arbiter_entity.vhd Normal file
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@ -0,0 +1,31 @@
entity memory_arbiter is
port (
clk : in std_logic;
reset : in std_logic;
fetch_enable : in std_logic;
fetch_ready : out std_logic;
fetch_address : in yarm_word;
fetch_instr_out : out yarm_word;
fetch_raise_exc : out std_logic;
fetch_exc_data : out exception_data_t;
datamem_enable : in std_logic;
datamem_ready : out std_logic;
datamem_instr_info_in : in instruction_info_t;
datamem_read_data : out yarm_word;
datamem_raise_exc : out std_logic;
datamem_exc_data : out exception_data_t;
-- little-endian memory interface, 4 byte address alignment
MEM_addr : out yarm_word;
MEM_read : out std_logic;
MEM_write : out std_logic;
MEM_ready : in std_logic;
MEM_byte_enable : out std_logic_vector(3 downto 0);
MEM_data_read : in yarm_word;
MEM_data_write : out yarm_word
);
end memory_arbiter;

20
sections/core/entities/multiplier_entity.vhd Normal file
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@ -0,0 +1,20 @@
entity multiplier is
generic (
-- A shorter than B: faster, but wider adder required
WIDTH_A : positive;
WIDTH_B : positive
--PARALLELISM : positive
);
port (
clk : in std_logic;
run : in std_logic;
valid : out std_logic;
mul_signed : in std_logic;
a : in std_logic_vector(WIDTH_A-1 downto 0);
b : in std_logic_vector(WIDTH_B-1 downto 0);
result : out std_logic_vector(WIDTH_A+WIDTH_B-1 downto 0)
);
end multiplier;

9
sections/core/entities/program_counter_entity.vhd Normal file
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@ -0,0 +1,9 @@
entity program_counter is
port (
clk : in std_logic;
reset : in std_logic;
operation : in pc_operation_t;
pc_in : in yarm_word;
pc_out : out yarm_word
);
end program_counter;

16
sections/core/entities/registers_entity.vhd Normal file
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@ -0,0 +1,16 @@
entity registers is
port (
clk : in std_logic;
read_enable : in std_logic;
write_enable : in std_logic;
addr_a : in register_addr_t;
addr_b : in register_addr_t;
addr_d : in register_addr_t;
data_a : out yarm_word;
data_b : out yarm_word;
data_d : in yarm_word
);
end registers;

22
sections/soc/soc.tex
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@ -143,4 +143,26 @@ The exact timing differs between models, so all periods can be customized using
% TODO % TODO
\subsection{External Bus}
Bridging the internal SoC bus with the external peripheral bus requires a few steps. For one, the external data bus is bidirectional, so tri-state outputs must be used on the FPGA. In addition, the internal bus arbitrates components using addresses alone, while the external bus uses chip enable signals and overlapping address spaces.
Due to a mistake in the adapter board layout, the nibbles of the address and data buses are reversed (MSB to LSB are pins 7 to 0 on the FPGA, but 3 to 0 followed by 7 to 4 on the board). Thanks to the completely arbitrary mapping of FPGA pins, this can be mitigated without using any additional resources.
\section{Testing}
\subsection{RISC-V Compliance Tests}
The RISC-V Compliance Test Suite\cite{riscv-compliance} can be used to empirically confirm the correct functionality of a RISC-V processor. It consists of a series of programs that perform some operations related to a specific feature, then write some result data to a memory region. This memory region is then compared to a ``golden signature'', which was produced by a processor implementation that is known to be correct.
The initial implementation of the compliance tests uncovered several bugs in the processor core:
\begin{itemize}
\item The bitshift instructions (SLL, SRL, SRA, etc.) must, according to the RISC-V standard, only use the lower 5 bits of the second operand as a shift offset. The implementation used all 31 bits instead, causing a test failure.
\item Reading a signed value of a size less than 32 bits from memory would not perform proper sign extension. For example, reading a byte value of 0xFF (-1) would result in an expanded machine word of 0x0000_00FF (255) instead of 0xFFFF_FFFF.
\item The \icode{SLTIU} (Set less than immediate; unsigned) instruction compares a given register with a constant provided as part of the instruction (the immediate). While the comparison is unsigned, the 12-bit immediate must be sign-extended as if it were a signed integer. The implementation wrongly assumed that the sign-extension should be unsigned as well.
\item The Instruction Set Manual specifies exceptions that must be raised when a misaligned memory access occurs. These exceptions were not yet implemented, but since the compliance tests check for them, the functionality was added to make the tests pass.
\end{itemize}
Since these tests are easily automated, they were added to the GitLab Continuous Integration (CI) configuration. Whenever a new git commit is pushed to GitLab, the tests are run automatically, and any failures are reported to the responsible committer via email.
\end{document} \end{document}

2
sections/vhdl_intro/vhdl_intro.tex
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@ -14,7 +14,7 @@ Other than a text editor, the following Free Software packages have to be instal
\item[\icode{ghdl}\cite{ghdl}] to analyze, compile, and simulate the design \item[\icode{ghdl}\cite{ghdl}] to analyze, compile, and simulate the design
\item[\icode{gtkwave}\cite{gtkwave}] to view the simulation waveform files \item[\icode{gtkwave}\cite{gtkwave}] to view the simulation waveform files
\item[\icode{yosys}\cite{yosys}] to synthesize the design \item[\icode{yosys}\cite{yosys}] to synthesize the design
\item[\icode{ghdlsynth-beta}\cite{yosys}] to synthesize the design \item[\icode{ghdlsynth-beta}\cite{ghdlsynth-beta}] to synthesize the design
\item[\icode{nextpnr-xilinx}\cite{nextpnr-xilinx}] to place and route the design \item[\icode{nextpnr-xilinx}\cite{nextpnr-xilinx}] to place and route the design
\item[\icode{Project X-Ray}\cite{prjxray}] for FPGA layout data and bitstream tools \item[\icode{Project X-Ray}\cite{prjxray}] for FPGA layout data and bitstream tools
\item[\icode{openFPGALoader}\cite{open-fpga-loader}] to load the bitstream onto the FPGA \item[\icode{openFPGALoader}\cite{open-fpga-loader}] to load the bitstream onto the FPGA