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Added morreeeee 

Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
This commit is contained in:
Tyrolyean 2020-03-23 10:04:40 +01:00
parent fe336cda09
commit 8a28b339ab
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GPG Key ID: 81EC9BAC5E9667C6
50 changed files with 72427 additions and 33465 deletions
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98
bibliographies/DP.bib
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@ -17,22 +17,114 @@
title = {DUAL 8-BIT MUTLIPLYING DIGITAL-TO-ANALOG CONVERTERS},
organization = {Texas Instruments Inc.},
year = {1987},
url = {http://www.komponenten.es.aau.dk/fileadmin/komponenten/Data_Sheet/Memory/IDT7201.pdf},
url = {https://www.ti.com/lit/ds/symlink/tlc7528.pdf},
}
@techreport{rs232,
type = {Standard},
key = {TIA-/EIA-232-F},
month = October,
month = Oct,
year = {1997},
title = {Interface Between Data Terminal Equipment and Data Circuit- Terminating Equipment Employing Serial Binary Data Interchange},
volume = {1997}
}
@Manual{max232,
month = February,
month = Feb,
year = {1989},
title = {MAX232x Dual EIA-232 Drivers/Receivers},
organization = {Texas Instruments Inc.},
url = {https://www.ti.com/lit/ds/symlink/max232.pdf}
}
@Manual{74hc374,
month = Feb,
year = {1998},
title = {High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered},
organization = {Texas Instruments Inc.},
url = {https://www.ti.com/lit/ds/schs183c/schs183c.pdf}
}
@Manual{74hc00,
month = Dec,
year = {1982},
title = {SNx4HC00 Quadruple 2-Input Positive-NAND Gates},
organization = {Texas Instruments Inc.},
url = {https://www.ti.com/lit/ds/symlink/sn74hc00.pdf}
}
@Manual{ad2,
month = Sep,
year = {2015},
title = {Analog Discovery 2™ Reference Manual},
organization = {Digilent, Inc.},
url = {https://reference.digilentinc.com/_media/reference/instrumentation/analog-discovery-2/ad2_rm.pdf}
}
@Manual{atmega2560,
month = Feb,
year = {2014},
title = {Atmel ATmega640/V-1280/V-1281/V-2560/V-2561/V},
organization = {Atmel Corporation},
url = {https://ww1.microchip.com/downloads/en/devicedoc/atmel-2549-8-bit-avr-microcontroller-atmega640-1280-1281-2560-2561_datasheet.pdf}
}
@techreport{iec60908,
type = {Standard},
key = {IEC 60908},
month = Sep,
year = {1987},
institution = {International Electrotechnical Commission},
title = {Compact disc digital audio system},
volume = {1987}
}
@book{audiob,
title = {The Audio Expert: Everything You Need to Know About Audio},
author = {Winer, Ethan},
publisher = {Focal Press},
year = {2013},
url = {https://books.google.com/books?id=TIfOAwAAQBAJ&pg=PA107#v=onepage&q=-%2010%20dbv&f=false}
}
@article{lvlshift,
title = {Taking It To Another Level: Making 3.3V Speak With 5V},
author = {Jenny List},
publisher = {Hackaday},
year = {2016},
month = Dec,
url = {https://hackaday.com/2016/12/05/taking-it-to-another-level-making-3-3v-and-5v-logic-communicate-with-level-shifters/}
}
@Manual{DB3S406F0L,
month = Mar,
year = {2010},
title = {Schottky Barrier Diode DB3S406F0L Silicon epitaxial planar type},
organization = {Panasonic},
url = {https://industrial.panasonic.com/content/data/SC/ds/ds4/DB3S406F0L_E.pdf}
}
@Manual{dunnet,
year = {1982},
title = {Dunnet Source Code},
organization = {Emacs},
author = {Ron Schnell},
url = {https://github.com/jwiegley/emacs-release/blob/master/lisp/play/dunnet.el}
}
@Manual{vt100,
year = {1979},
title = {VT100 SERIES TECHNICAL MANUAL},
organization = {Digital Equipment Corporation},
url = {https://vt100.net/docs/vt100-tm/ek-vt100-tm-002.pdf}
}
@techreport{ascii,
type = {Standard},
key = {RFC 20},
month = Oct,
year = {1969},
institution = {Network Working Group},
title = {ASCII Format for Network Interchange},
volume = {1969},
url = {https://tools.ietf.org/pdf/rfc20.pdf}
}

1
code/dac/saw_fifo/src/main.c
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@ -72,7 +72,6 @@ int main(){
int routine(){
for(size_t i = 0; i < 256; i++){
//PORTF = (0xFF & ((uint8_t)(sinf(i*3.141592654/255)/3.141592654*255)));
PORTF = (0xFF & i);
PORTK &= ~(0x01<<0);
PORTK |= (0x01<<0);

8
code/dac/saw_fifo_backplane/src/main.c
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@ -115,11 +115,6 @@ int main(){
_delay_us(100);
PORTL &= ~(1<<MR_SHIFT);
/* Generate sine table */
for(size_t i = 0; i < 256; i++){
sine_table[i] = 0xFF&((int)((sin(i/((double)255)*(3.141592*2))*127.5+127.5)));
}
sei();
/* Enable the hardware watchdog. In case the microcontroller fails to
* finish it's task within the specified time, the watchdog will reset
@ -139,11 +134,10 @@ int main(){
int routine(){
for(uint8_t i = 0; i < 0xFF; i++){
write_to_dac(i%2, sine_table[i]);
write_to_dac(0x00, i);
}
write_to_dac(0x00, 0x00);
write_to_dac(0x01, 0x00);
_delay_ms(10);
return 0;

70
code/dac/sine_fifo_backplane/Makefile Normal file
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@ -0,0 +1,70 @@
MKDIR_P := mkdir -p
CP := cp
MV := mv
CC := avr-gcc
CCC := avr-g++
RM_RF = rm -rf
OCPY := avr-objcopy
AVRDUDE := avrdude
PORT := /dev/ttyACM0
#PORT := usb
#BOARD := atmega328p
BOARD := atmega2560
#PROGRAMMER := arduino
PROGRAMMER := usbasp
#PROGBOARD := m328p
PROGBOARD := m2560
BAUD_RATE_PROG := 115200
FLASH_CMD := $(AVRDUDE) -b $(BAUD_RATE_PROG) -p $(PROGBOARD) -D -P $(PORT) -c $(PROGRAMMER)
AVRSIZE := avr-size
AVRSIZE_FLAGS := -C --mcu=$(PROGBOARD)
# directories
CWD := $(realpath .)
BINDIR := $(CWD)/bin
BUILDDIR := $(CWD)/build
SRCDIR := $(CWD)/src
INCLUDEDIR := $(CWD)/include
# flas
CFLAGS := -mmcu=$(BOARD) -Os -I$(INCLUDEDIR) -Wall -Wextra
LDFLAGS := -mmcu=$(BOARD)
# target files
DIRS_TARGET := $(BINDIR) $(BUILDDIR)
TARGET := $(BINDIR)/mc.hex
TARGET_ELF := $(BINDIR)/mc.elf
SRCFILES := $(wildcard $(SRCDIR)/*.c)
OBJFILES := $(patsubst $(SRCDIR)/%.c,$(BUILDDIR)/%.o,$(SRCFILES))
# fancy targets
all: directories $(TARGET)
directories: $(DIRS_TARGET)
# less fancy targets
$(DIRS_TARGET):
$(MKDIR_P) $@
$(TARGET) : $(TARGET_ELF)
$(OCPY) -O ihex -j .text -j .data $^ $@
$(TARGET_ELF): $(OBJFILES)
$(CC) $(LDFLAGS) -o $@ $^
$(AVRSIZE) $(AVRSIZE_FLAGS) $@
$(BUILDDIR)/%.o: $(SRCDIR)/%.c
$(CC) $(CFLAGS) -c -o $@ $<
flash: $(TARGET)
# For atmega 2560
$(FLASH_CMD) -e -U hfuse:w:0xD9:m -U lfuse:w:0xDF:m -U efuse:w:0xFF:m -U flash:w:$^:i -U efuse:w:0xfa:m
# For atmega 328p:
#$(FLASH_CMD) -e -U hfuse:w:0xD9:m -U efuse:w:0xFF:m -U lfuse:w:0xDF:m -U flash:w:$^:i -U efuse:w:0xfd:m
# If unknown or no fuse bits available over programmer
#$(FLASH_CMD) -U flash:w:$^:i
$(FLASH_CMD) -U flash:v:$^:i
clean:
$(RM_RF) $(DIRS_TARGET)

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code/dac/sine_fifo_backplane/bin/mc.elf Executable file
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code/dac/sine_fifo_backplane/bin/mc.hex Normal file
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@ -0,0 +1,140 @@
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code/dac/sine_fifo_backplane/build/main.o Normal file
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code/dac/sine_fifo_backplane/src/main.c Normal file
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@ -0,0 +1,153 @@
/* Copyright © 2020 tyrolyean
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define F_CPU 16000000UL
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <avr/wdt.h>
#include <util/delay.h>
#include <avr/interrupt.h>
#define BUS_HOLD_US 1
/* Shift values inside the PORTK Register */
#define WR_SHIFT 1
#define RD_SHIFT 2
#define MR_SHIFT 0
#define CS_SHIFT 4
uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
void get_mcusr(void) \
__attribute__((naked)) \
__attribute__((section(".init3")));
void get_mcusr(void)
{
mcusr_mirror = MCUSR;
MCUSR = 0;
wdt_disable();
}
void set_addr(uint8_t addr){
PORTK = addr;
return;
}
uint8_t sine_table[256];
void write_to_dac(uint8_t addr, uint8_t data){
set_addr(addr);
DDRF = 0xFF;
PORTL &= ~(1<<WR_SHIFT);
PORTF = data;
PORTL &= ~(1<<CS_SHIFT);
_delay_us(BUS_HOLD_US); /*Wait for the data and signal lanes to become stable*/
PORTL |= 1<<CS_SHIFT;
set_addr(0x00);
PORTL |= 1<<WR_SHIFT;
PORTF = 0x00;
return;
}
uint8_t read_from_dac(uint8_t addr){
uint8_t data = 0x00;
set_addr(addr);
DDRF = 0x00;
PORTF = 0x00;
PORTL &= ~(1<<RD_SHIFT);
PORTL &= ~(1<<CS_SHIFT);
_delay_us(BUS_HOLD_US); /* Wait for the data and signal lanes to become stable*/
data = PINF;
PORTL |= 1<<CS_SHIFT;
set_addr(0x00);
PORTL |= 1<<RD_SHIFT;
DDRF = 0xFF;
PORTF = 0x00;
_delay_us(BUS_HOLD_US); /*Wait for the data and signal lanes to become stable*/
return data;
}
int routine();
int main(){
/* Disable interrupts during initialisation phase */
cli();
/* Setup Data Direction Registers and populate with sane default
values */
DDRF = 0xFF; /* Data Bus */
DDRK = 0xFF; /* Address Bus */
DDRL = 0xFF; /* Control Bus */
PORTF = 0x00;
PORTK = 0x00;
PORTL = 0x00;
/* Cleanly reset the dac uart */
PORTL |= (1<<WR_SHIFT);
PORTL |= (1<<RD_SHIFT);
PORTL |= (1<<CS_SHIFT);
PORTL |= (1<<MR_SHIFT);
_delay_us(100);
PORTL &= ~(1<<MR_SHIFT);
/* Generate sine table */
uint8_t sine_table[256];
for(size_t i = 0; i < 256; i++){
sine_table[i] = 0xFF&((int)((sin(i/((double)255)*(3.141592*2))*
127.5+127.5)));
}
sei();
/* Enable the hardware watchdog. In case the microcontroller fails to
* finish it's task within the specified time, the watchdog will reset
* the atmel cookie.
*/
wdt_enable(WDTO_1S);
while(1){
wdt_reset();
if(routine() < 0){
}
}
return 0;
}
int routine(){
for(uint8_t i = 0; i < 0xFF; i++){
write_to_dac(i%2, sine_table[i]);
}
write_to_dac(0x00, 0x00);
write_to_dac(0x01, 0x00);
_delay_ms(10);
return 0;
}

9
code/textadv/src/dac.c
View File

@ -59,8 +59,12 @@ uint8_t read_from_dac(uint8_t addr){
}
void feed_dac(){
/* Internal counter for positioning inside the array */
/* Internal counter for positioning inside the currently playing
* waveform */
static uint8_t threash = 0x00;
/* Used to generate the desired frequency offset if the waveform should
* be made "longer" --> the frequency made lower from baseline
*/
static int16_t freq_delay_cnt = 0x00;
switch(dac_mode){
@ -74,8 +78,7 @@ void feed_dac(){
case DAC_MODE_SINE:
/* Generates a sine from a predetermined sine table in program
* space
*/
* space */
for(uint8_t i = 0; i < (0xFF/2); i++){
write_to_dac(1,
pgm_read_byte(&sine_table[threash]));

6
code/textadv/src/sound.c
View File

@ -216,7 +216,9 @@ const struct tone_t intro_track[] PROGMEM =
const struct tone_t *current_track = NULL;
/* Loops a track indefinitely and changes voices according to predefined tables.
* A new track resets the internal state. A voice with a length of 0ms */
* A new track resets the internal state. A voice with a length of 0ms is used
* to mark the end of a track and continue at the beginning
*/
void update_sound(){
static uint16_t audio_time = 0;
@ -246,12 +248,10 @@ void update_sound(){
memcpy_P(&current_tone,&(current_track[tone_pointer]),
sizeof(current_tone));
}
dac_mode = current_tone.waveform;
dac_frequency_deviation = current_tone.frequency_deviation;
audio_time = 0x00;
tone_pointer++;

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\babel@toc {ngerman}{}
\babel@toc {ngerman}{}
\babel@toc {english}{}
\contentsline {figure}{\numberline {1}{\ignorespaces Atari PBI Pinout;Source: \url {https://www.atarimagazines.com}\relax }}{2}{figure.caption.1}%
\contentsline {figure}{\numberline {2}{\ignorespaces Digilent Analog Discovery 2;Source: \url {https://www.sparkfun.com/}\relax }}{4}{figure.caption.2}%
\contentsline {figure}{\numberline {3}{\ignorespaces Layout of the DIN41612 Connectors on the Backplane\relax }}{5}{figure.caption.3}%
\contentsline {figure}{\numberline {4}{\ignorespaces Measurement at around 1MHz bus clock on MS1\relax }}{6}{figure.caption.4}%
\contentsline {figure}{\numberline {5}{\ignorespaces The case with installed backplane\relax }}{7}{figure.caption.5}%
\contentsline {figure}{\numberline {6}{\ignorespaces PC-16550D Pinout\cite {pc16550}\relax }}{8}{figure.caption.6}%
\contentsline {figure}{\numberline {7}{\ignorespaces The schematic of the UART Module\relax }}{10}{figure.caption.7}%
\contentsline {figure}{\numberline {8}{\ignorespaces Measurement of the 1.8432 MHz Output on J1\relax }}{11}{figure.caption.8}%
\contentsline {figure}{\numberline {9}{\ignorespaces Measurement of a character transmission before and after MAX-232\relax }}{12}{figure.caption.9}%
\contentsline {figure}{\numberline {10}{\ignorespaces Pinout of the RJ-45 Plug; Src: \url {https://www.wti.com/}\relax }}{12}{figure.caption.10}%
\contentsline {figure}{\numberline {11}{\ignorespaces Measurement of a character echo\relax }}{13}{figure.caption.11}%
\contentsline {figure}{\numberline {12}{\ignorespaces Transmission of character A via the 16550 UART\relax }}{16}{figure.caption.12}%
\contentsline {figure}{\numberline {i}{\ignorespaces Atari PBI Pinout;Source: \url {https://www.atarimagazines.com}\relax }}{2}{figure.caption.1}%
\contentsline {figure}{\numberline {ii}{\ignorespaces Digilent Analog Discovery 2;Source: \url {https://www.sparkfun.com/}\relax }}{4}{figure.caption.2}%
\contentsline {figure}{\numberline {iii}{\ignorespaces Layout of the DIN41612 Connectors on the Backplane\relax }}{5}{figure.caption.3}%
\contentsline {figure}{\numberline {iv}{\ignorespaces Measurement at around 1MHz bus clock on MS1\relax }}{6}{figure.caption.4}%
\contentsline {figure}{\numberline {v}{\ignorespaces The case with installed backplane\relax }}{7}{figure.caption.5}%
\contentsline {figure}{\numberline {vi}{\ignorespaces PC-16550D Pinout\cite {pc16550}\relax }}{8}{figure.caption.6}%
\contentsline {figure}{\numberline {vii}{\ignorespaces The schematic of the UART Module\relax }}{10}{figure.caption.7}%
\contentsline {figure}{\numberline {viii}{\ignorespaces Measurement of the 1.8432 MHz Output on J1\relax }}{11}{figure.caption.8}%
\contentsline {figure}{\numberline {ix}{\ignorespaces Measurement of a character transmission before and after MAX-232\relax }}{12}{figure.caption.9}%
\contentsline {figure}{\numberline {x}{\ignorespaces Pinout of the RJ-45 Plug; Src: \url {https://www.wti.com/}\relax }}{12}{figure.caption.10}%
\contentsline {figure}{\numberline {xi}{\ignorespaces Measurement of a character echo\relax }}{13}{figure.caption.11}%
\contentsline {figure}{\numberline {xii}{\ignorespaces Transmission of character A via the 16550 UART\relax }}{16}{figure.caption.12}%
\contentsline {figure}{\numberline {xiii}{\ignorespaces TLC-7528 Pinout\cite {tlc7528}\relax }}{18}{figure.caption.13}%
\contentsline {figure}{\numberline {xiv}{\ignorespaces IDT-7201 Pinout\cite {idt7201}\relax }}{19}{figure.caption.14}%
\contentsline {figure}{\numberline {xv}{\ignorespaces TLC-7528 in voltage modet\cite {tlc7528}\relax }}{20}{figure.caption.15}%
\contentsline {figure}{\numberline {xvi}{\ignorespaces Measurement of a generated SAW signal via the TLC7528\relax }}{20}{figure.caption.16}%
\contentsline {figure}{\numberline {xvii}{\ignorespaces The schematic of the DAC Module\relax }}{21}{figure.caption.17}%
\contentsline {figure}{\numberline {xviii}{\ignorespaces Measurement of a generated SAW signal with the FIFO Empty flag\relax }}{23}{figure.caption.18}%
\contentsline {figure}{\numberline {xix}{\ignorespaces A transmission between the FIFO and the DAC\relax }}{24}{figure.caption.19}%
\contentsline {figure}{\numberline {xx}{\ignorespaces A fifo store operation in contrast to the load operation\relax }}{24}{figure.caption.20}%
\contentsline {figure}{\numberline {xxi}{\ignorespaces Storage and retrieval of a sine to and from the FIFO\relax }}{26}{figure.caption.21}%
\contentsline {figure}{\numberline {xxii}{\ignorespaces Measuremet of the generated sine from the sine LUT on DACA and DACB\relax }}{26}{figure.caption.22}%
\contentsline {figure}{\numberline {xxiii}{\ignorespaces 3.3V to 5V conversion using the level shifter\relax }}{27}{figure.caption.23}%
\contentsline {figure}{\numberline {xxiv}{\ignorespaces 5V to 3.3V conversion using the level shifter\relax }}{28}{figure.caption.24}%
\contentsline {figure}{\numberline {xxv}{\ignorespaces The internal schematics of the level shifter\cite {lvlshift}\relax }}{29}{figure.caption.25}%
\contentsline {figure}{\numberline {xxvi}{\ignorespaces The internal clamping diodes of the Analog Discovery 2\cite {ad2}\relax }}{30}{figure.caption.26}%
\contentsline {figure}{\numberline {xxvii}{\ignorespaces The output of an example track part 1\relax }}{40}{figure.caption.27}%
\contentsline {figure}{\numberline {xxviii}{\ignorespaces The output of an example track part 2\relax }}{41}{figure.caption.28}%
\babel@toc {ngerman}{}
\babel@toc {english}{}

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\T1/pxss/m/n/12 Diese Di-plom-ar-beit be-schäf-tigt sich mit der Ar-beits-wei-s
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\contentsline {lstlisting}{\numberline {2}16550 INIT routines and single char transmission}{15}{lstlisting.2}%
\contentsline {lstlisting}{\numberline {3}16550 character echo}{16}{lstlisting.3}%
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\contentsline {lstlisting}{\numberline {V}Sine LUT Generation}{25}{lstlisting.5}%
\contentsline {lstlisting}{\numberline {VI}DAC Sine Generation}{25}{lstlisting.6}%
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\input{preamble.tex}
\begin{document}
\selectlanguage{ngerman}
% Correct numeral usage in footnotes, figures and listings
\renewcommand{\thefootnote}{\Alph{footnote}}
\renewcommand{\thelstlisting}{\Roman{lstlisting}}
\renewcommand{\thefigure}{\roman{figure}}
%/*Header-Einstellung*/
\pagestyle{fancy}
@ -22,6 +26,7 @@
\begin{center}
\begin{minipage}{\linewidth}
\begin{center}
\vspace*{-21mm}
\HtlHeader{}
\vspace*{-14mm}
@ -94,9 +99,10 @@ interpreted as gender neutral.
\addcontentsline{toc}{section}{Kurzfassung/Abstract}
\input{sections/abstract.tex}
\newpage
\subsection*{Projektergebnis\markboth{}{Projektergebnis}}
\addcontentsline{toc}{section}{Projektergebnis}
%\input{sections/ergebnis.tex} TODO
\subsection*{Result\markboth{}{Result}}
\addcontentsline{toc}{section}{Result}
\input{sections/result.tex}
\newpage
%====================================================================================
\pagestyle{plain}
\selectlanguage{english}
@ -126,12 +132,9 @@ interpreted as gender neutral.
\DP\input{sections/DP/MEAS_TEST/main.tex}
\DP\input{sections/DP/CASE_BACKPLANE/main.tex}
\DP\input{sections/DP/UART/main.tex}
\section{Textadventure}
\DP\input{sections/DP/dac/main.tex}
\DP\input{sections/DP/fpga_interface/main.tex}
\DP\input{sections/DP/textadv/main.tex}
\clearpage
%\MR\input{sections/Kapitel/MR/Aufgabengeneration.tex}
\clearpage
%\MR\input{sections/Kapitel/MR/EntwicklungAufgaben.tex}

33
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@ -6,7 +6,7 @@
\contentsline {section}{Kurzfassung/Abstract}{ii}{Doc-Start}%
\babel@toc {ngerman}{}
\babel@toc {ngerman}{}
\contentsline {section}{Projektergebnis}{iii}{Doc-Start}%
\contentsline {section}{Result}{iii}{Doc-Start}%
\babel@toc {english}{}
\contentsline {section}{\numberline {1}Task description}{1}{section.1}%
\contentsline {subsection}{\numberline {1.1}Hardware}{1}{subsection.1.1}%
@ -33,12 +33,35 @@
\contentsline {subsubsection}{\numberline {2.7.4}Demonstration Software}{13}{subsubsection.2.7.4}%
\contentsline {paragraph}{Transmit code}{13}{figure.caption.11}%
\contentsline {paragraph}{Echo code}{16}{figure.caption.12}%
\contentsline {section}{\numberline {3}Textadventure}{17}{section.3}%
\contentsline {subsection}{\numberline {3.1}General Implementation details}{18}{subsection.3.1}%
\contentsline {subsection}{\numberline {2.8}Audio Digital-Analog-Converter}{17}{subsection.2.8}%
\contentsline {subsubsection}{\numberline {2.8.1}TLC 7528 Dual R2R Ladder DAC}{18}{subsubsection.2.8.1}%
\contentsline {subsubsection}{\numberline {2.8.2}IDT7201 CMOS FIFO Buffer}{18}{subsubsection.2.8.2}%
\contentsline {subsubsection}{\numberline {2.8.3}Theory verfication}{19}{subsubsection.2.8.3}%
\contentsline {subsubsection}{\numberline {2.8.4}Schematics}{20}{subsubsection.2.8.4}%
\contentsline {paragraph}{Element Description}{22}{figure.caption.17}%
\contentsline {paragraph}{NE55 Clock Source}{22}{figure.caption.17}%
\contentsline {subsubsection}{\numberline {2.8.5}Demonstration Software}{23}{subsubsection.2.8.5}%
\contentsline {paragraph}{SAW Generator}{23}{subsubsection.2.8.5}%
\contentsline {paragraph}{Sine Generator}{25}{lstnumber.4.11}%
\contentsline {section}{\numberline {3}Addressing DACA and DACB}{26}{section.3}%
\contentsline {subsection}{\numberline {3.1}FPGA to Hardware interface}{27}{subsection.3.1}%
\contentsline {subsubsection}{\numberline {3.1.1}Measurement error}{29}{subsubsection.3.1.1}%
\contentsline {section}{\numberline {4}Textadventure}{30}{section.4}%
\contentsline {subsection}{\numberline {4.1}General Implementation details}{30}{subsection.4.1}%
\contentsline {subsubsection}{\numberline {4.1.1}General definitions and pinout of the AVR}{30}{subsubsection.4.1.1}%
\contentsline {subsubsection}{\numberline {4.1.2}Read and Write routines}{32}{subsubsection.4.1.2}%
\contentsline {subsubsection}{\numberline {4.1.3}UART and DAC update polling}{32}{subsubsection.4.1.3}%
\contentsline {subsection}{\numberline {4.2}DAC sound generation}{33}{subsection.4.2}%
\contentsline {subsubsection}{\numberline {4.2.1}DAC modes}{33}{subsubsection.4.2.1}%
\contentsline {subsubsection}{\numberline {4.2.2}Tones and Tracks}{37}{subsubsection.4.2.2}%
\contentsline {subsubsection}{\numberline {4.2.3}Track switching}{42}{subsubsection.4.2.3}%
\contentsline {subsection}{\numberline {4.3}User command interpretation}{42}{subsection.4.3}%
\contentsline {subsubsection}{\numberline {4.3.1}Command structure and pasring}{42}{subsubsection.4.3.1}%
\contentsline {subsubsection}{\numberline {4.3.2}Command parameters}{44}{subsubsection.4.3.2}%
\babel@toc {ngerman}{}
\contentsline {section}{\numberline {4}Erkl"arung der Eigenst"andigkeit der Arbeit}{20}{section.4}%
\contentsline {section}{\numberline {5}Erkl"arung der Eigenst"andigkeit der Arbeit}{46}{section.5}%
\babel@toc {english}{}
\contentsline {section}{\numberline {I\tmspace +\thickmuskip {.2777em}}List of Figures}{I}{section.1}%
\contentsline {section}{\numberline {II\tmspace +\thickmuskip {.2777em}}List of Tables}{I}{section.2}%
\contentsline {section}{\numberline {III\tmspace +\thickmuskip {.2777em}}Listings}{I}{section.3}%
\contentsline {section}{Anhang}{II}{section.3}%
\contentsline {section}{Anhang}{IV}{section.3}%

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5
sections/DP/MEAS_TEST/main.tex
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@ -8,7 +8,7 @@ required.
Measurements were performed, if not noted otherwise, with the Analog Discovery
2 from Digilent as it has 16bit digital I/O Pins as well a a Waveform generator
and 2 differential oszilloscope inputs. These were for all nescessary
and 2 differential oszilloscope inputs\cite{ad2}. These were for all nescessary
measurements enough. Though due to the size and construction of the device,
which can be seen in figure \ref{fig:ad2}
errors wer encountered while performing the measurements. These are noted on
@ -25,7 +25,8 @@ occurance.
All testing was performed with an Atmel ATMega2560 due to it's large amount
of I/O pins, 5V I/O which is the more common voltage level on CMOS
peripherials, way of addressing pins (8 at a time) and availability. All
peripherials, way of addressing pins (8 at a time) and availability.
\cite{atmega2560} All
testing software was written for this ATMega and compiled using the avr-gcc
from the GNU-Project.

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\subsection{Audio Digital-Analog-Converter}
A digital to analog converter takes a digital number and converts it to a
analog signal. The output of one such conversion is called a sample. With
enough samples per second various different waveforms can be produced which,
when amplified and put onto a speaker, can be heared by the human ear as a tone.
With various tones in series a melody can be produced, which is what the DAC in
this implementation does.
\subsubsection{TLC 7528 Dual R2R Ladder DAC}
The TLC 7528 is a Dual output Parallel input R2R Ladder DAC with a maximum
sample rate of 10MHz\cite{tlc7528} and which (should be) is monotonic over the
entire D/A Conversion Range. The TLC-7528 was the only component chosen, where
availability was not a factor, but rather due to it's design.It is the cheapest
dual R2R Ladder dac which takes \textbf{PARALLEL} input, which was an important
feature, because the backbone of the project is its parallel bus. Further the
DAC was developed for audio aplications\cite{tlc7528} obvious and
the TLC-7528 was the only IC available as DIP
\footnote{DIP... Dual Inline Package}, of which the pinout can be seen in figure
\ref{fig:tlc7528_pinout}
\begin{figure}[H]
\centering
\includesvg[height=.3\textheight, angle=0]{pics/slas062e_pinout.svg}
\caption{TLC-7528 Pinout\cite{tlc7528}}
\label{fig:tlc7528_pinout}
\end{figure}
\subsubsection{IDT7201 CMOS FIFO Buffer}
The IDT7201 is an asychronous CMOS FIFO, which means that it can be read with
a completely independant speed from which it is written and vice versa. It has
9 bit words, which can be seen in figure \ref{fig:idt7201_pinout}, and can
store up to 256 words\cite{idt7201}. It is used as a buffer
to store data describing the targeted waveform in order to free time on the
parallel bus for interaction with the 16550 UART.
\begin{figure}[H]
\centering
\includesvg[height=.3\textheight, angle=0]{pics/idt7201_pinout.svg}
\caption{IDT-7201 Pinout\cite{idt7201}}
\label{fig:idt7201_pinout}
\end{figure}
\subsubsection{Theory verfication}
Before tests of the complete unit were conducted, the functionality of the
device and the validity of the knowledge of operations were performed. For that
the DAC was directl connected to the ATMega without the FIFO infront of it.
A saw was generated on only the DACA channel, which was put into voltage mode
as described in the datasheet\cite{tlc7528} and seen in figure
\ref{fig:tlc7528_volt}. After the result seen in \ref{fig:tlc7528_saw_nonlin}
was found a lot of effort was put in to determine the source of the heavy noise,
however no obvious conclusion can be made, execpt that it comes from the DAC
itself and is consistant over whatever frequency used. A damaged IC could be
the reason or a sloppy production progress. Filters can be used to reduce the
noise, however this was not done in this thesis, as the generated audio does
not seem to suffer from these non-linearities as badly as when measured
standalone.
\begin{figure}[H]
\centering
\includesvg[height=.3\textheight, angle=0]{pics/slas062e_volt.svg}
\caption{TLC-7528 in voltage modet\cite{tlc7528}}
\label{fig:tlc7528_volt}
\end{figure}
\begin{figure}[H]
\begin{tikzpicture}
\begin{axis}[
ylabel=REFA Voltage,
xlabel=Time,
grid=both,
minor tick num=5,
xmin=-2.030599999999999e-05,
xmax=0.000598364,
width=\textwidth,
height=0.4\textheight]
\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200210_saw_nonlin.csv};
\end{axis}
\end{tikzpicture}
\caption{Measurement of a generated SAW signal via the TLC7528}
\label{fig:tlc7528_saw_nonlin}
\end{figure}
\subsubsection{Schematics}
Based on the descriptions in the datasheets the schematic in figure
\ref{fig:schem_dac} was developed.
\begin{figure}[H]
\centering
\includegraphics[height=.65\textheight, angle=-90]{schem_pdf/dac.pdf}
\caption{The schematic of the DAC Module}
\label{fig:schem_dac}
\end{figure}
\paragraph{Element Description}
Diodes D1 through D4 are used as OR-Gates in conjunction with R1 and R2 to
generate the $\lnot MODRD$ and $\lnot MODWR$ signals for the D Flip-Flop
\footnote{74HC374\cite{74hc374}} and FIFO respectively, by these formulas:
$\lnot MODRD = \lnot RD \lor \lnot MS2$
$\lnot MODWR = \lnot WR \lor \lnot MS2$
On a read access, the output enable of the D-Latch becomes low, which writes
the status bits of the FIFO onto the data bus. C1, C2 and C3 are for stability
reasons and are good practice, similar to the UART module. 74HC00 is a quad
NAND-Gate\cite{74hc00} which is only used for inversion, chosen, like the
74HC374, for availability reasons. The A part of the NAND-Gate inverts the $MR$
signal from the bus to a $\not MR$ signal as the FIFOs reset is low active.
The B part of the NAND-Gate inverts the FIFO Empty flag. It's output is
connected to the $\lnot WR$ input of the DAC, which means that the DAC doesn't
convert the input anymore, if the FIFO Empty flag is set to low.
The NE555 generates the audio clock signal, which should be the double of
44.1kHz\footnote{Because we have 2 output channels} as 44.1kHz is the standard
samling rate of CD-Audio\cite{iec60908}. Resistors R9 and R10 togehter with C7
form the Oscillator part of the NE55. C4 is for stability reasons and doesn't
define the frequency of the oscillator.
The generated clock is used for the $\lnot R$ of the FIFO and inverted on the
DAC, which makes the data available on the output before being stored into the
DAC as it receives the signal to store the data after the FIFO makes it
available on the bus.
The DAC is operated in voltage mode as described in \ref{fig:tlc7528_volt},
with it's voltage source beeing available at either 3.472Vpp for professional
audio or 0.894Vpp for consumer audio, as defined per convention.\cite{audiob}
The voltage source can be controlled via Jumper JP1.
C5 and C6 together with the load resistance on the audio jack form a high pass
with a cutoff frequency of
$f_C = \frac{1}{2\pi R C} = \frac{1}{2\times \pi\times 10K\Omega\times 100\mu F} = 0.159154943Hz$
which should cover the hearable spectrum. The high pass was needed to generate
a positive and negative half of the wave form, as the DC-Offset with a frequency
of 0Hz is orders of magnitudes lower than the $f_C$ of the highpass gets
filtered away.
R7 and R8 have been installed in order to unload the capacitors after device
poweroff.
\paragraph{NE55 Clock Source}
Though used as a clovk source, the NE555 is a bad clock source if a stable
clock is needed, because it varies widely with temperature, preasure and aging
elements. A better solution would have been a quartz which is divided down to
the desired frequency, whichwas what CD Drives used to do, but more commonly in
modern CD Drives, an ASIC with internal PLL is used, thus the required quartz
can no longer be sourced.
\subsubsection{Demonstration Software}
\paragraph{SAW Generator}
To prove read and write access from the D Flip-Flop and the FIFO are working,
the same saw signal has been generated as in figure \ref{fig:tlc7528_saw_nonlin}
, however the signal was put into the FIFO and not the DAC directly. The
resulting saw wave can be seen in figure \ref{fig:tlc7528_saw_fifo} together
with the FIFO Empty flag. The FIFO Empty flag, as explained before, is inverted
and starts/ends the complete D/A conversion, until further data is received.
\begin{figure}[H]
\begin{tikzpicture}
\begin{axis}[
ylabel=REFA Voltage,
xlabel=Time,
grid=both,
minor tick num=5,
xmin=0.02023862769230769,
xmax=0.02642198769230769,
width=\textwidth,
height=0.4\textheight]
\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200308fifo_44_1_saw_withfifoempty.csv};
\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200308fifo_44_1_saw_withfifoempty.csv};
\legend{REFA,$\lnot EF$}
\end{axis}
\end{tikzpicture}
\caption{Measurement of a generated SAW signal with the FIFO Empty flag}
\label{fig:tlc7528_saw_fifo}
\end{figure}
The time difference betwen a stor and complete write cycle can be seen in figure
\ref{fig:fifo_dac_store}, while the figure \ref{fig:fifo_dac} shows the
transmission between dac and fifo in more detail.
\begin{figure}[H]
\centering
\includegraphics[width=\textwidth, angle=0]{meas/20200308fifo_44_1_cnt.png}
\caption{A transmission between the FIFO and the DAC}
\label{fig:fifo_dac}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=\textwidth, angle=0]{meas/20200308fifo_44_1_saw.png}
\caption{A fifo store operation in contrast to the load operation}
\label{fig:fifo_dac_store}
\end{figure}
The initialisation routines and read/write operations for the DAC module are
basically the same as for the UART module, and have thus been ommitted. They
can be seen in listing \ref{lst:16550-transmit} and partially in listing
\ref{lst:16550-transmit}.
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:dac_saw}, caption={SAW Generation for the DAC with FIFO},
style=cstyle, firstline=134, lastline=144]
{code/dac/saw_fifo_backplane/src/main.c}
\paragraph{Sine Generator}
As a further example a sine was generated and played on the DAC. The ATMega
itself is not powerful enough to generate the sine on the fly, therefore a
lookup-table had to be generated, which can be seen in listing
\ref{lst:dac_sine_lut}. How the data is transmitted to the FIFO can be seen
in listing \ref{lst:dac_sine} and figure \ref{fig:fifo_sine_store} and the
resulting sine on both output channels can be seen in figure
\ref{fig:sine_dacab}.
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:dac_sine_lut}, caption={Sine LUT Generation},
style=cstyle, firstline=118, lastline=123]
{code/dac/sine_fifo_backplane/src/main.c}
The look-up table has a size of 256, which is the maximum value an 8 bit integer
can take. This size was chosen to make operation faster as it only takes
one cycle to load an array value into a register and another one to store it
into the GPIO register. The sine table in further examples was pre-genrated on
the compiling host to reduce startup time. The mothod shown in listing
\ref{lst:dac_sine_lut} is not fast due to the lack of a floating point unit
on the AVR. \cite{atmega2560}
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:dac_sine}, caption={DAC Sine Generation},
style=cstyle, firstline=141, lastline=152]
{code/dac/sine_fifo_backplane/src/main.c}
\begin{figure}[H]
\centering
\includegraphics[width=\textwidth, angle=0]{meas/20200310sine_dac.png}
\caption{Storage and retrieval of a sine to and from the FIFO}
\label{fig:fifo_sine_store}
\end{figure}
\begin{figure}[H]
\begin{tikzpicture}
\begin{axis}[
ylabel=Channel Voltage,
xlabel=Time,
grid=both,
minor tick num=5,
xmin=-0.001746707777777778,
xmax=0.001774992222222222,
width=\textwidth,
height=0.4\textheight]
\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200310sine_dac_osz.csv};
\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200310sine_dac_osz.csv};
\legend{DACA,DACB}
\end{axis}
\end{tikzpicture}
\caption{Measuremet of the generated sine from the sine LUT on DACA and DACB}
\label{fig:sine_dacab}
\end{figure}
\section{Addressing DACA and DACB}
The DAC used has 2 output channels which can be selected by the
$\lnot DACA/DACB$ pin as seen in figure \ref{fig:tlc7528_pinout}. This pin was
mapped to bit 0 of the address bus in order to make use of it. Bit 8 on the fifo
was used to store the bit. It was not implemented with half the bus clock to
make both channels independent of each other. This however uses more time on the
backend because it means the fifo is used up at twice the speed. No current
example makes use of this, but it may be used in future examples and
implementations on this unit.
On the audio jack DACA is mapped to the right channel and DACB to the left
channel.

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\subsection{FPGA to Hardware interface}
To make the Hardware work with the FPGA's 3.3V I/O, level shifter have been
installed and a FPGA module was built. This module maps the IO/Pins in a similar
way to the ATMega 2560 used in examples before. The bidirectional 5V<->3.3V
logic level converters have been obtained on amazon, and have not been well
documented. Their functionality has been tested and verified in both directions,
which can be seen in figures \ref{fig:3v35v} and \ref{fig:5v3v3}. The schematic
has also been determined through measurements with a multimeter and the
schematic in figure \ref{fig:schem_lvlshift} shows similar resistor values in
the same configuration \cite{lvlshift}.
\begin{figure}[H]
\begin{tikzpicture}
\begin{axis}[
ylabel=Lane Voltage,
xlabel=Time,
grid=both,
xmin=-1.151135531135531e-06,
xmax=5.488864468864469e-06,
minor tick num=5,
width=\textwidth,
height=0.5\textheight]
\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200301shift3v35v.csv};
\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200301shift3v35v.csv};
\legend{LV-Side,HV-Side}
\end{axis}
\end{tikzpicture}
\caption{3.3V to 5V conversion using the level shifter}
\label{fig:3v35v}
\end{figure}
The in figure \ref{fig:3v35v} shown output on the HV side, corresponds with the
schematics in figure \ref{fig:schem_lvlshift} where it can be seen that the
resistor R2 is loading the bus capacitance to a 5V high state.
\begin{figure}[H]
\begin{tikzpicture}
\begin{axis}[
ylabel=Lane Voltage,
xlabel=Time,
grid=both,
xmin=-7.427469135802469e-07,
xmax=3.567253086419753e-06,
minor tick num=5,
width=\textwidth,
height=0.5\textheight]
\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200301shift5v3v3.csv};
\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200301shift5v3v3.csv};
\legend{LV-Side,HV-Side}
\end{axis}
\end{tikzpicture}
\caption{5V to 3.3V conversion using the level shifter}
\label{fig:5v3v3}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[height=.4\textheight, angle=0]{pics/bidirectonal-mosfet-level-shifter.png}
\caption{The internal schematics of the level shifter\cite{lvlshift}}
\label{fig:schem_lvlshift}
\end{figure}
\subsubsection{Measurement error}
During an attempt to measure wether the level shifters in the final module were
working, a measurement between the LV and the HV side showed only a difference
of 0.7V. After some troubleshooting, it was found that the Analog Discovery has
clamping diodes against the 3.3V rail shown in figure \ref{fig:ad2_diode}. These
diodes produce the 0.7V offset and prevent the parallel bus from rising to
5V when a digial I/O pin of the Analog Discovery 2 is connected to the bus.
\cite{DB3S406F0L}.
\begin{figure}[H]
\centering
\includegraphics[height=.4\textheight, angle=0]{pics/ad2_dio.png}
\caption{The internal clamping diodes of the Analog Discovery 2\cite{ad2}}
\label{fig:ad2_diode}
\end{figure}

256
sections/DP/textadv/main.tex
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@ -1,3 +1,5 @@
\section{Textadventure}
To illustrate how the components work together and can be used in various
different applications, a small text-adventure with audio effects was written in
C. The main goal was to show the capabilities of even small systems like the
@ -5,6 +7,8 @@ one developed.
\subsection{General Implementation details}
\subsubsection{General definitions and pinout of the AVR}
Like the before examples, the textadventure was implemented on an ATMega2560
and uses 3 different Registers for transmission: PORTF, PORTK and PORTL for
address bus, data bus and control bus respectively, as can be seen in listing
@ -15,11 +19,259 @@ address bus, data bus and control bus respectively, as can be seen in listing
label={lst:textadv-avr.h}, caption={The avr.h header file},
columns=flexible, style=cstyle]{./code/textadv/include/avr.h}
The in listing \ref{lst:textadv-avr.h} shown defines MR_SHIFT, WR_SHIFT,
The in listing \ref{lst:textadv-avr.h} shown preprocessor macros
MR_SHIFT, WR_SHIFT,
RD_SHIFT, CS_UART_SHIFT and CS_DAC_SHIFT are used to indicate the position of
the corresponding control lines inside the control bus register. All other
shift values are the same bitordering in input as in output.
The BUS_HOLD_US is used to tell the avr how many microsecons it takes for the
data bus to be latched into input register of the devices on write or how long
it takes for the data bus to become stable on read.
it takes for the data bus to become stable on read. A delay of less than 1
microsecond is not possible due to limitations of the AVR and the bus capacity,
which increases the BER\footnote{BER...Bit Error Ratio} to a level which effects
regular operation.
\subsubsection{Read and Write routines}
The set_addr function is the same as in the UART example code in listing
\ref{lst:16550-general} and has therefore been omitted, execept for its definiton
in the avr.h file in listing \ref{lst:textadv-avr.h}. The read and write
functions for the UART module and the DAC module are the same as in the example
code for the modules and have been ommited therefore as well.
\subsubsection{UART and DAC update polling}
The AVR constantly polls the DAC and UART modules for updates as can be seen in
listing \ref{lst:textadv-routine}. The routine\_MODULE functions poll their
respective modules for updates as can be seen in listings
\ref{lst:textadv-routine-uart} and \ref{lst:textadv-routine-dac}. When a
character is received, it is stored inside a bufer array and regular operation
continues. If the $\lnot EF$ status bit is set in a read from the dac, the
feed\_dac function is called which stores 256 bytes into the DAC and regular
operation continues.
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-routine}, caption={The routine function looped by the main},
columns=flexible, style=cstyle, firstline=105, lastline=110]
{code/textadv/src/main.c}
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-routine-uart}, caption={The routine function for the UART},
columns=flexible, style=cstyle, firstline=105, lastline=118]
{code/textadv/src/16550.c}
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-routine-dac}, caption={The routine function for the DAC},
columns=flexible, style=cstyle, firstline=197, lastline=203]
{code/textadv/src/dac.c}
\subsection{DAC sound generation}
\subsubsection{DAC modes}
The DAC can produced any waveform described by 8 bit unsigned PCM code. Though
possible to feed predefined waveforms into the DAC, the AVR doesn't have enough
onboard memory to store more than a few seconds of these waveforms.
For example to store one second of 8 bit unsigned PCM Code at 2 times 44.1KHz
sampling rate of the DAC, the AVR would have to store
$s = 2 \times 44100\frac{Bytes}{s}*1s = 2\times 44100 Bytes = 88.2KB$, but it
has only a total of 256KB of onboard flash\cite{atmega2560} which makes for a
total track lengh of $ t = \frac{256KB}{88.2\frac{KB}{s}} = 2.9s$ with only
one track.
Therefore the AVR generates the audio on runtime. To do that it has 6 builtin
modes in which it can run, as can be seen in listing
\ref{lst:textadv-dac-modes}:
\begin{enumerate}
\item{silent mode:}
The DAC produces no output at all and is completely silent.
\item{sine mode:}
The DAC produces a sine with a specific frequency and an
amplitude of 255.
\item{square mode:}
The DAC produces a square wave with a specific frequency and an
amplitude of 255.
\item{saw mode:}
The DAC produces a saw wave with a specific frequency and an
amplitude of 255.
\item{noise mode:}
The DAC produces a pseudo-random white-noise with a maximum
amplitude of 255.
\item{triangle mode:}
The DAC produces a triangle wave with a specific frequency and
an amplitude of 255.
\end{enumerate}
To perform these tasks the DAC takes two parameters, again seen in listing
\ref{lst:textadv-dac-modes}:
\begin{itemize}
\item{A frequency deviation:}
Used to tell the dac how much the desired frequency deviates
from the base frequency of each waveform.
\item{A mode:}
Used to tell it which waveform to generate
\end{itemize}
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-dac-modes}, caption={The DAC operation modes},
columns=flexible, style=cstyle, firstline=25, lastline=38]
{code/textadv/include/dac.h}
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-dac-gen}, caption={The DAC waveform generation code},
columns=flexible, style=cstyle, firstline=61, lastline=198]
{code/textadv/src/dac.c}
\subsubsection{Tones and Tracks}
A sound track inside the textadventure consists of independent tones. A tone is
a waveform at a specific frequency played for a specific time. To perform the
specific time functionality independant of DAC speed, an ISR
\footnote{ISR...Interrupt Service Routine} on the AVR was used to change to
the next tone every millisecond. A track is an array of tones with an end marker
tone at the end which is a tone with a length of 0ms. The end marker tone tells
the ISR to reset to the initial tone. The ISR can be seen in listing
\ref{lst:textadv-isr} and the sound update function, which actually updates the
current tone and is responsible for playing a track in listing
\ref{lst:textadv-upsnd}. The output of an example track can be seen in
figures \ref{fig:textadv_track_ex1} and \ref{fig:textadv_track_ex2}.
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-isr}, caption={The ISR which fires every millisecond},
columns=flexible, style=cstyle, firstline=31, lastline=34]
{code/textadv/src/interrupt.c}
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-upsnd}, caption={The sound update function},
columns=flexible, style=cstyle, firstline=218, lastline=262]
{code/textadv/src/sound.c}
\newpage
\begin{figure}[H]
\begin{tikzpicture}
\begin{axis}[
ymin=-0.5025374538865546,
ymax=-.0580652077731092,
ylabel=Time,
xlabel=Track output,
ymajorgrids=true,
width=\textwidth,
height=0.98\textheight]
\addplot table [x=c1, y=t, col sep=comma, mark=none] {meas/20200315audio_multiple_voices.csv};
\addplot table [x=c2, y=t, col sep=comma, mark=none] {meas/20200315audio_multiple_voices.csv};
\legend{DACA,DACB}
\end{axis}
\end{tikzpicture}
\caption{The output of an example track part 1}
\label{fig:textadv_track_ex1}
\end{figure}
\newpage
\begin{figure}[H]
\begin{tikzpicture}
\begin{axis}[
ymin=-.0580652077731092,
ymax=0.4444722461134454,
ylabel=Time,
xlabel=Track output,
ymajorgrids=true,
width=\textwidth,
height=0.98\textheight]
\addplot table [x=c1, y=t, col sep=comma, mark=none] {meas/20200315audio_multiple_voices.csv};
\addplot table [x=c2, y=t, col sep=comma, mark=none] {meas/20200315audio_multiple_voices.csv};
\legend{DACA,DACB}
\end{axis}
\end{tikzpicture}
\caption{The output of an example track part 2}
\label{fig:textadv_track_ex2}
\end{figure}
\subsubsection{Track switching}
To switch tracks on different actions, there is a map of tracks associated with
rooms. Every room has an associated track, where the association can change on
actions performed, which allows for a game atmosphere change. Track changes are
performed outside the ISR, which could theoretically result in a race condition
where the ISR would load a faulty track for 1ms if the track change was not
performed fast enough, but this is prevented by disabling global interrupts
during a track change.
\subsection{User command interpretation}
\subsubsection{Command structure and pasring}
As in other text adventures \cite{dunnet} a command consits of one line of
input terminated by a newline or line feed character \textbackslash n.
The carriage return character which is sometimes transmitted with a line
feed character is not parsed in this text adventure. Incoming character
parsing can be seen in listings \ref{lst:textadv-uart-recv} and
\ref{lst:textadv-ingest}.
As one command is parsed each part is required to be separated by an empty
space character which is ascii code 32 \cite{ascii}. The first part of the given
input is then compared to an array of actions a user can perform, for example
use or search, as can be seen in listing \ref{lst:textadv-parsecmd}
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-uart-recv}, caption={The UART char receive code},
columns=flexible, style=cstyle, firstline=105, lastline=118]
{code/textadv/src/16550.c}
In listing \ref{lst:textadv-uart-recv} the comment echo back can be seen. The
write\_char function before it writes the last received character back to the
terminal which sent it. This is done to write what the user typed out to the
terminal as otherwise it would not be seen what has been typed on any VT100
compatiable terminal\cite{vt100} or terminal emulator.
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-ingest}, caption={The character ingest function},
columns=flexible, style=cstyle, firstline=71, lastline=79]
{code/textadv/src/game.c}
The in listing \ref{lst:textadv-ingest} shown branch overrides the last received
character with 0x00 which is ascii NUL and decrements the buffer pointer by one
if the received character was 0x7F. 0x7F is the ADCII DELETE character
\cite{ascii} which instructs the receiving end that the last received character
was a mistake and should be purged. This is also what a vt100 compiant terminal
emulator sends when the backspace or delete key is pressed \cite{vt100}.
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-parsecmd}, caption={The command parsing function},
columns=flexible, style=cstyle, firstline=31, lastline=69]
{code/textadv/src/game.c}
\subsubsection{Command parameters}
Command paramters are interpreted as the string that follows the action
and the space behind it. As can be seen in the case for ACTION\_USE in
listing \ref{lst:textadv-perfact} the use item function is passed the
command buffer\footnote{which is an address in memory} plus the length of the
entered command plus one for the space. So the string starting at the passed
address should match the start address of the parameter. If no parameter is
supplied, the address should point to a character containing ASCII NUL, which
marks the end of a string, bcause after comand parsing the string is overwritten
with zeros as seen in listing \ref{lst:textadv-parsecmd}.
\lstinputlisting[language=C,frame=trBL,
breaklines=true, breakautoindent=true, formfeed=\newpage,
label={lst:textadv-perfact}, caption={The command execution routine},
columns=flexible, style=cstyle, firstline=81, lastline=120]
{code/textadv/src/game.c}

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The project was fully implemented with all functionality originally targeted.
The system has been tested and verified and all example code have been
documented and tested as running. Implementations in hardware were made in
open-source programs and the RISC-V processor can compile using an open source
toolchain. The completed project can be found on the USB stick which accompanies
this thesis, or in the git repositories at
\url{https://git.it-syndikat.org/tyrolyean/dipl.git} and
\url{https://gitlab.com/YARM-project/}.

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This is XeTeX, Version 3.14159265-2.6-0.999991 (TeX Live 2019/Arch Linux) (preloaded format=xelatex 2020.3.10) 19 MAR 2020 17:00
This is XeTeX, Version 3.14159265-2.6-0.999991 (TeX Live 2019/Arch Linux) (preloaded format=xelatex 2020.3.10) 22 MAR 2020 23:57
entering extended mode
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