Removed svg inkscape
Signed-off-by: Tyrolyean <tyrolyean@tyrolyean.net>
This commit is contained in:
parent
8569677921
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main.tex
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main.tex
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@ -126,7 +126,7 @@ geschlechtsunabh"angig verstanden werden soll.
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\clearpage
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\pagestyle{fancy}
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\section{Hardware peripherials}
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\section{Hardware peripherals}
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\DP\input{sections/DP/PARALLELBUS/main.tex}
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\DP\input{sections/DP/MEAS_TEST/main.tex}
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\DP\input{sections/DP/CASE_BACKPLANE/main.tex}
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@ -12,7 +12,7 @@ peripherials schematics and a working implementation in the hardware building
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style of the hackerspace should be built. All nescessary hardware will be
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provided by the Hackerspace. If possible already present hardware should be
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used, if impossible new one will be ordered. All schematics should, where
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possible be written in open-source software such as Kicad or GNU-EDA.
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possible, be constructed in Free software such as Kicad or GNU-EDA.
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If possible software-examples should be written as well, though the complexity
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of these are coupled to the time left to spend on the project. Software should
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@ -52,3 +52,134 @@ die Meilensteintermine wurden vom Betreuer festgelegt.
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\label{tab:mst_plank}
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\end{table}
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\subsubsection{Work time reference}
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Table \ref{tab:plank_work} shows the times worked.
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\begin{longtable}{| l | c | p{100mm} |}
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\hline
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\textbf{Date} & \textbf{Duration [h]} & \textbf{Task}\\
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\hline
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\hline
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2019-09-06 & 4.25 & start of thesis document \\
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\hline
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2019-09-07 & 2.25 & planning of thesis \\
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\hline
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2019-09-20 & 1 & planning part two, input into database \\
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\hline
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2019-09-23 & 0.5 & corrections in database \\
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\hline
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2019-09-25 & 0.5 & discussions with supervisor about deadlines\\
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\hline
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2019-09-27 & 0.25 & reformatting and discussion about database entry\\
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\hline
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2019-10-11 & 2 & tests and high level design for MS1\\
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\hline
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2019-10-12 & 3.75 & gather PDFs for MS1\\
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\hline
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2019-10-16 & 2.5 & tests and high level design for MS1\\
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\hline
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2019-10-17 & 2.5 & tests and high level design for MS1\\
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\hline
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2019-10-20 & 4.25 & tests and high level design for MS1\\
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\hline
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2019-10-22 & 3.5 & Finalisation tests and high level design for MS1\\
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\hline
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2019-12-08 & 4.75 & Download thesis template and implement\\
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\hline
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2020-01-03 & 6.75 & Planning and early schematics of serial module\\
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\hline
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2020-01-04 & 2 & Parallel port layout\\
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\hline
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2020-01-08 & 3.75 & Serial console breadboard test\\
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\hline
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2020-01-11 & 2.5 & Attempting interaction with 16550\\
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\hline
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2020-01-18 & 4.5 & Attempting interaction with 16550 nailing down errors\\
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\hline
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2020-01-18 & 3 & Attempting interaction with 16550\\
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\hline
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2020-02-25 & 1 & Help partner with hosting tar.gz file\\
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\hline
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2020-01-26 & 6.25 & Attempting interaction with 16550 no output\\
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\hline
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2020-02-01 & 3 & Attempting interaction with 16550 quartz doesn’t oscillate\\
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\hline
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2020-02-07 & 5.5 & Attempting to make 1.8432MHz oscillators oscillate\\
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\hline
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2020-02-08 & 3 & Oscillation succeeded… finaly\\
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\hline
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2020-02-09 & 7.75 & Transmit character in serial via 16550\\
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\hline
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2020-02-10 & 4 & Serial console eurocard\\
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\hline
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2020-02-11 & 5 & Serial console and arduino eurocard\\
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\hline
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2020-02-12 & 5 & Serial console and arduino eurocard\\
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\hline
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2020-02-13 & 4 & Serial console and arduino eurocard testing\\
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\hline
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2020-02-14 & 6 & Serial console and arduino eurocard code\\
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\hline
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2020-02-15 & 3.5 & Serial console and arduino eurocard code\\
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\hline
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2020-02-18 & 3.5 & ECHO! Program\\
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\hline
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2020-02-19 & 3.5 & DAC schematic and breadboard beginning\\
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\hline
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2020-02-20 & 2.25 & DAC driver simulation attempt\\
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\hline
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2020-03-01 & 3.25 & Level shifter test and verification\\
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\hline
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2020-03-04 & 2 & DAC fifo breadboard\\
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\hline
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2020-03-08 & 7.5 & breadboard final test DAC and FIFO and eurocard\\
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\hline
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2020-03-10 & 4.75 & DAC module test and sine generation code\\
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\hline
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2020-03-11 & 4.25 & textadventure start\\
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\hline
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2020-03-12 & 4.25 & textadventure polling dac and 16550\\
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\hline
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2020-03-13 & 4.5 & finalisation of everything in school COVID-19\\
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\hline
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2020-03-14 & 5 & textadventure DAC mode implementation\\
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\hline
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2020-03-15 & 4 & textadventure sound routines\\
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\hline
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2020-03-17 & 4 & textadventure gameplay\\
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\hline
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2020-03-18 & 6 & documentation\\
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\hline
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2020-03-19 & 4 & documentation\\
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\hline
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2020-03-20 & 3 & documentation\\
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\hline
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2020-03-21 & 1 & textadventure gamplay\\
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\hline
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2020-03-22 & 0.5 & textadventure gamplay\\
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\hline
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2020-03-23 & 6.25 & documentation\\
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\hline
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2020-03-24 & 6.75 & documentation\\
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\hline
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2020-03-25 & 7.25 & documentation\\
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\hline
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2020-03-26 & 7 & documentation\\
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\hline
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2020-03-27 & 5.75 & documentation\\
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\hline
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2020-03-28 & 4.5 & documentation\\
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\hline
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2020-03-29 & 6.5 & documentation\\
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\hline
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2020-03-30 & 9.75 & documentation\\
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\hline
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2020-03-31 & 0 & documentation\\
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\hline
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\hline
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2020-04-01 & \textbf{SUM} & 229.5h\\
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\hline
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\caption{Work time reference}
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\label{tab:plank_work}
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\end{longtable}
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@ -1,6 +1,6 @@
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Aus der Projektimplementierung konnten viele Lehren gezogen werden. Messungen
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welche mittels ses Analog Discoverys durchgeführt wurden sind bis zu ungefähr
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1MHz frequenz gut zu gebrauchen werden danach jedoch sehr stark fehlerhaft. Alle
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welche mittels des Analog Discovery durchgeführt wurden sind bis zu ungefähr
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1MHz Frequenz gut zu gebrauchen werden danach jedoch sehr stark fehlerhaft. Alle
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Bauteile in THT Bauform zu verwenden vereinfachte Messungen am Steckbrett
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erheblich, jedoch werden diese bei hohen Frequenzen unzuverlässig. Viele
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Implementationsdetails wurden durch mündlich übergebene Hinweise verbessert
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@ -1,8 +1,8 @@
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\subsection{Backplane}
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To connect the modules to the microprocessor, many pins need to be connected
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straight through. For this purpose a backplane was chosen where DIN41612
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connectors can be used. These connectors were chosen for their large pin count
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straight through. For this purpose a backplane with DIN41612
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connectors is beeingused . These connectors are used for their large pin count
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(96 pins) and their availability. The backplane connects all 96-pins straight
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through. With the 6 outer left and right pins connected for VCC and ground
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as can be seen in Figure \ref{fig:schem_back_conn}.
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@ -1,7 +1,7 @@
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\subsection{Testing and Measurement}
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For functional testing and verification of implementation goals measurements
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needed to be performed in various different ways and testing software was
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needed to be performed in various different ways, and testing software was
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required.
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\subsubsection{Measurements}
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@ -25,7 +25,7 @@ occurance.
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All testing was performed with an Atmel ATMega2560 due to it's large amount
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of I/O pins, 5V I/O, which is the more common voltage level on CMOS
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peripherials, way of addressing pins (8 at a time) and availability.
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peripherals, way of addressing pins (8 at a time) and availability.
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\cite{atmega2560} All
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testing software was written for this ATMega and compiled using the avr-gcc
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from the GNU-Project.
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@ -38,7 +38,7 @@ for all indends and purposes, only a breakout of the ATMega 2560 and has only
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been used in that way. No parts of the Arduino\texttrademark IDE or other parts
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of the Arduino\texttrademark software suite have been used, as they consume too
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much memory and the abstraction models used are not compatiable with building
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processor peripherials.
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processor peripherals.
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\begin{figure}[H]
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\centering
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@ -1,7 +1,7 @@
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\subsection{Parallel bus}
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The core part of the hardware is the interface between the microprocessor and
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the hardware peripherials. This bus is delivering data in parallel and is
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the hardware peripherals. This bus is delivering data in parallel and is
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therefore named the ``parallel bus``. This bus has 3 different sub-parts:
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\begin{enumerate}
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@ -55,8 +55,8 @@ therefore easy to program with. The address bus is unidirectional.
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\subsubsection{Data Bus}
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The data bus contains the actual data to be stored to and read from registers.
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The data bus is, as well on most systems a multiple of 16 bits wide, but for the
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same reasons as the data bus, was shrunk down in our case to 8 bits. The data
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The data bus is as well on most systems a multiple of 16 bits wide, but for the
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same reasons as the data bus is shrunk down in our case to 8 bits. The data
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bus is bidirectional.
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\subsubsection{Control Bus}
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@ -90,25 +90,25 @@ in our case is 5 bits wide and consists of:
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\paragraph{Master Reset}
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A high level on the $MR$ lane signals to the peripherials that a reset of all
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A high level on the $MR$ lane signals to the peripherals, that a reset of all
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registers and states should occure. This is needed for the serial console and
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the DAC.
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\paragraph{Write Not}
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A low level on the $\lnot WR$ lane signals the corresponding modules that the
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A low level on the $\lnot WR$ lane signals the corresponding modules, that the
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data on
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the data bus should be written to the register on the address specified from the
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address bus.
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\paragraph{Read Not}
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A low level on the $\lnot RD$ lane signals the corresponding modules that the
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A low level on the $\lnot RD$ lane signals the corresponding modules, that the
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data
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from the register specified by the address on the address bus should be written
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to the data bus.
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\paragraph{Module Select 1 and 2 Not}
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A low level on one of these lines signals the corresponding module that the
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A low level on one of these lines signals the corresponding module, that the
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data on address data and the control lines is meant for it.
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\paragraph{Sepearation of $\lnot RD$/$\lnot WR$ and$\lnot MS1$/$\lnot MS2$}
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@ -121,7 +121,7 @@ point in time. Therefore these signals have not been combined.
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\subsection{Von Neumann Archtiecture}
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The term ``von Neumann architecture`` referrs to a type of computer architecture
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The term ``von Neumann architecture`` refers to a type of computer architecture
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which referres to almost any modern computer system. It describes the in this
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thesis used Human input and output parts and the general workings of modern
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processors with the ALU\footnote{ALU...arithmetic logic unit} or the CA
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@ -143,7 +143,7 @@ This can be applied to the hardware implemented in this thesis, as well as
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other general computing systems. The EDVAC, which his thesis referres to, was a
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computer developed for military purposes. Much like the EDVAC, the CPU in this
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thesis is responsible for arithemtic operations and code interpetation. The
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peripherials are what is referred to as the input and output devices in his
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peripherals are what is referred to as the input and output devices in his
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report. Though the for examples used ATMega2650 utilizes a harvard architecture
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``In order to maximize performance and parallellism``\cite[p.11]{atmega2560} the
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more general descriptions of computational operations still apply to this
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@ -5,10 +5,11 @@ systems, and even today on server machines, this is done via a serial console.
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On this serial console characters are transmitted in serial, which means bit
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by bit over the same line. The voltage levels used in these systems vary from
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5V to 3.3V or +-10V. The most common standard for these voltage levels is the
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former RS-232\footnote{RS... Recommended Standard} or as it should be called
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former RS-232\footnote{RS... Recommended Standard}, or as it should be called
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now, TIA-\footnote{TIA...Telecommunications Industry
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Association}/EIA-\footnote{EIA.. Electronic Industries Alliance}232.\cite{rs232}
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Voltage-levels ,as per TIA-/EIA- standard, are not practical to handle over short
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Voltage-levels, as per TIA-/EIA-232 standard, are not practical to handle over
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short
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distances however, so other voltages are used on most interface chips
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and need to be converted.
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@ -342,7 +342,7 @@ on the AVR. \cite{atmega2560}
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\end{figure}
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\section{Addressing DACA and DACB}
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\subsubsection{Addressing DACA and DACB}
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The DAC used has 2 output channels which can be selected by the
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$\lnot DACA/DACB$ pin as seen in figure \ref{fig:tlc7528_pinout}. This pin was
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@ -1,12 +1,12 @@
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\subsection{Hardware peripherials}
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\subsection{Hardware peripherals}
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Planning of the peripherials was done based on the information provided on large
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Planning of the peripherals was done based on the information provided on large
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parts by David Oberhollenzer. A lot of his advice contributed heavily to the
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direction the development went.
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\subsubsection{Peripherial selection}
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The selection of the hardware peripherials was done based on implementation
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The selection of the hardware peripherals was done based on implementation
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difficulty, common use in computer systems, relevance in current times and
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wether they were fitting for demonstrative purposes.
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@ -79,13 +79,13 @@ understanding of IIC as it is only known in technical fields.
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\paragraph{Utility analysis}
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Among the above mentioned processor peripherials from the criteria mentioned
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Among the above mentioned processor peripherals from the criteria mentioned
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before a utility analysis was performed. To do this different point have been
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credited for the criteria mentioned which can be seen in Table
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\ref{tab:utility_base}. The multipliers in Table \ref{tab:utility_base} have
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been applied to the points and the sums in Table \ref{tab:utility_result}
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resulted. Based on this
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result the DAC and Serial Communication interface were chosen as peripherials.
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result the DAC and Serial Communication interface were chosen as peripherals.
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\begin{table}[H]
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\centering
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@ -106,7 +106,7 @@ result the DAC and Serial Communication interface were chosen as peripherials.
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\end{tabular}
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}
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\caption{utility analysis base points for peripherials}
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\caption{utility analysis base points for peripherals}
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\label{tab:utility_base}
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\end{table}
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@ -128,7 +128,7 @@ result the DAC and Serial Communication interface were chosen as peripherials.
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\end{tabular}
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\caption{utility analysis multipliers for peripherials}
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\caption{utility analysis multipliers for peripherals}
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\label{tab:utility_mul}
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\end{table}
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@ -157,6 +157,6 @@ result the DAC and Serial Communication interface were chosen as peripherials.
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\end{tabular}
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}
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\caption{utility analysis results for peripherials}
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\caption{utility analysis results for peripherals}
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\label{tab:utility_result}
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\end{table}
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@ -13,15 +13,15 @@ RISC-V32I base instruction set. Aufgrund der starken Verwendung von Englisch im
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Software- und Hardwarebereich wurde diese Diplomarbeit in Englisch verfasst,
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wodurch
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ebenfalls die Lesbarkeit erhöht wird. Die entstandene Dokumentation soll für
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Menschen mit einem grundlegenden Verständnis von Elektronik sowie der Hardware-
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Menschen mit einem grundlegenden Verständnis für Elektronik sowie der Hardware-
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Beschreibungssprache VHDL verständlich sein.
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\end{otherlanguage}
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\\\\
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This diploma thesis deals with the operation of processors and their
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corresponding peripherials in modern and traditional forms. It attempts to
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corresponding peripherals in modern and traditional forms. It attempts to
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illustrate the structure of a computersystem in hard- and software. To reach
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this goal a RISC-V32I processor has been implemented in VHDL on a XILINX FPGA
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as well as some peripherials bound to the parallel bus. These peripherials
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as well as some peripherals bound to the parallel bus. These peripherals
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include a 2-channel 8-bit Digital to analog converter as well as a TIA-/EIA-232
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compliant serial interface. Due to the common use of english in the hardware and
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software engineering field this thesis is written in english, which
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@ -4,15 +4,15 @@ from scratch has come up. Multiple suggestions on how to implement it and the
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scope of the project were gathered. Originally the goal of the project was to
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have a computer which would consist of seperate plug-in cards on each of which
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one instruction would reside. This would debunk the mystery behind the ``black
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box`` which processors today are.
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box`` which processors are today.
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Most processors today are only documented on the execution of their programs and
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not on their internals. The projects aim was later redirected, due to concerns
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about the difficulty of the project, to build a processor in VHDL instead. After
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several months of implementation time the project was split into two parts: the
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peripherials and the core processor. During the development processes and after
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peripherals and the core processor. During the development processes and after
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rememberingthe original goal to make a processor understandable, the
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peripherials changed from being implemented in VHDL back to hardware, which came
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peripherals changed from being implemented in VHDL back to hardware, which came
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with increased work but would result in a far more understandable final product.
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The decision for a RISC-V based processor was made at the beginning of the
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@ -1,18 +1,17 @@
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The project is fully implemented with all functionality originally targeted.
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The system has been tested and verified. All example codes have been
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documented and tested. Hardware implementations were created using
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open-source programs, while the RISC-V processor can be compiled with an open
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source
|
||||
toolchain. The completed project can be found on the USB stick which accompanies
|
||||
Free software programs, while the RISC-V processor can be compiled with a Free
|
||||
toolchain. The completed project can be found on the USB stick, which accompanies
|
||||
this thesis, or in the git repositories at
|
||||
\url{https://git.it-syndikat.org/tyrolyean/dipl.git} and
|
||||
\url{https://gitlab.com/YARM-project/}. The completed hardware peripherials can
|
||||
\url{https://gitlab.com/YARM-project/}. The completed hardware peripherals can
|
||||
be seen in Figure \ref{fig:all_mod}
|
||||
|
||||
\begin{figure}[H]
|
||||
\centering
|
||||
\includegraphics[width=\textwidth, angle=180]{pics/all_mod}
|
||||
\caption{An overview of the hardware peripherials}
|
||||
\caption{An overview of the hardware peripherals}
|
||||
\label{fig:all_mod}
|
||||
\end{figure}
|
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Reference in New Issue