Update core diagram

This commit is contained in:
Xiretza 2020-03-30 23:38:10 +02:00
parent c15a3ec470
commit 637573fd43
Signed by: xiretza
GPG key ID: E51A6C6A1EB378ED
3 changed files with 8 additions and 10 deletions

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@ -6,7 +6,13 @@
The core implements the \instrset{} architecture as specified by the RISC-V standard~\cite{riscv-spec-unprivileged}. The core implements the \instrset{} architecture as specified by the RISC-V standard~\cite{riscv-spec-unprivileged}.
It is constructed according to the traditional RISC pipeline: \begin{figure}[h]
\includegraphics[width=\textwidth]{core_diagram.png}
\caption{Block diagram of the CPU core}
\label{fig:core-diagram}
\end{figure}
As can be seen in \ref{fig:core-diagram}, it is constructed according to the traditional stages of a RISC pipeline:
\begin{description} \begin{description}
\item[Fetch] fetches the next instruction from memory. \item[Fetch] fetches the next instruction from memory.
@ -16,14 +22,6 @@ It is constructed according to the traditional RISC pipeline:
\item[Writeback] stores a potential result value from Execute or Memory stages to the destination register. \item[Writeback] stores a potential result value from Execute or Memory stages to the destination register.
\end{description} \end{description}
\subsection{Overview}
\begin{figure}
%\includegraphics[width=\textwidth]{core_diagram.png}
% TODO
\caption{Block diagram of the CPU core}
\end{figure}
\subsection{Control} \subsection{Control}
\entityheader{control} \entityheader{control}

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