Update Hello World example, demonstrate synthesis
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14 changed files with 206 additions and 315 deletions
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*.o
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*.o
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*.ghw
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*.ghw
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*.gtkw
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work-*.cf
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work-*.cf
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svg-inkscape/
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svg-inkscape/
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vhdl_intro/vhdl/.gitignore
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vhdl_intro/vhdl/.gitignore
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*.json
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*.fasm
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*.frames
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*.bit
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counter_tb
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vhdl_intro/vhdl/counter.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter is
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port (
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clk : in std_logic;
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reset : in std_logic;
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enable : in std_logic;
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direction : in std_logic;
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count_out : out std_logic_vector(7 downto 0)
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);
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end counter;
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architecture behaviour of counter is
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signal count : unsigned(7 downto 0) := (others => '0');
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begin
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proc: process(clk)
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begin
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if reset then
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count <= (others => '0');
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elsif rising_edge(clk) and enable = '1' then
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if direction = '1' then
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count <= count + 1;
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else
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count <= count - 1;
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end if;
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end if;
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end process;
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count_out <= std_logic_vector(count);
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end behaviour;
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vhdl_intro/vhdl/counter.xdc
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set_property LOC D9 [get_ports clk]
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set_property LOC C9 [get_ports reset]
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set_property LOC A8 [get_ports enable]
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set_property LOC C11 [get_ports direction]
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set_property LOC F6 [get_ports count_out[0]]
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set_property LOC J4 [get_ports count_out[1]]
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set_property LOC J2 [get_ports count_out[2]]
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set_property LOC H6 [get_ports count_out[3]]
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set_property LOC H5 [get_ports count_out[4]]
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set_property LOC J5 [get_ports count_out[5]]
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set_property LOC T9 [get_ports count_out[6]]
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set_property LOC T10 [get_ports count_out[7]]
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set_property IOSTANDARD LVCMOS33 [get_ports clk]
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set_property IOSTANDARD LVCMOS33 [get_ports reset]
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set_property IOSTANDARD LVCMOS33 [get_ports enable]
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set_property IOSTANDARD LVCMOS33 [get_ports direction]
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set_property IOSTANDARD LVCMOS33 [get_ports count_out[0]]
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set_property IOSTANDARD LVCMOS33 [get_ports count_out[1]]
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set_property IOSTANDARD LVCMOS33 [get_ports count_out[2]]
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set_property IOSTANDARD LVCMOS33 [get_ports count_out[3]]
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set_property IOSTANDARD LVCMOS33 [get_ports count_out[4]]
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set_property IOSTANDARD LVCMOS33 [get_ports count_out[5]]
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set_property IOSTANDARD LVCMOS33 [get_ports count_out[6]]
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set_property IOSTANDARD LVCMOS33 [get_ports count_out[7]]
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vhdl_intro/vhdl/counter_tb.gtkw
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@ -0,0 +1,30 @@
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||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
|
||||||
|
[*] Fri Mar 6 16:40:57 2020
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/xiretza/Nextcloud/School/Diplomarbeit/Diplomschrift/vhdl_intro/vhdl/counter_tb.ghw"
|
||||||
|
[dumpfile_mtime] "Fri Mar 6 16:40:14 2020"
|
||||||
|
[dumpfile_size] 814
|
||||||
|
[savefile] "/home/xiretza/Nextcloud/School/Diplomarbeit/Diplomschrift/vhdl_intro/vhdl/counter_tb.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 910 543
|
||||||
|
[pos] 357 86
|
||||||
|
*-25.819012 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[treeopen] top.
|
||||||
|
[treeopen] top.counter_tb.
|
||||||
|
[treeopen] top.counter_tb.uut.
|
||||||
|
[sst_width] 221
|
||||||
|
[signals_width] 169
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 125
|
||||||
|
@28
|
||||||
|
top.counter_tb.uut.clk
|
||||||
|
top.counter_tb.uut.reset
|
||||||
|
top.counter_tb.uut.enable
|
||||||
|
top.counter_tb.uut.direction
|
||||||
|
@200
|
||||||
|
-
|
||||||
|
@24
|
||||||
|
#{top.counter_tb.count_out[7:0]} top.counter_tb.count_out[7] top.counter_tb.count_out[6] top.counter_tb.count_out[5] top.counter_tb.count_out[4] top.counter_tb.count_out[3] top.counter_tb.count_out[2] top.counter_tb.count_out[1] top.counter_tb.count_out[0]
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
||||||
71
vhdl_intro/vhdl/counter_tb.vhd
Normal file
71
vhdl_intro/vhdl/counter_tb.vhd
Normal file
|
|
@ -0,0 +1,71 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
entity counter_tb is
|
||||||
|
end counter_tb;
|
||||||
|
|
||||||
|
architecture test of counter_tb is
|
||||||
|
signal clk, reset, enable, direction : std_logic;
|
||||||
|
signal s_count_out : std_logic_vector(7 downto 0);
|
||||||
|
|
||||||
|
signal count_out : unsigned(7 downto 0);
|
||||||
|
begin
|
||||||
|
uut: entity work.counter
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
reset => reset,
|
||||||
|
enable => enable,
|
||||||
|
direction => direction,
|
||||||
|
|
||||||
|
count_out => s_count_out
|
||||||
|
);
|
||||||
|
|
||||||
|
count_out <= unsigned(s_count_out);
|
||||||
|
|
||||||
|
simulate: process
|
||||||
|
begin
|
||||||
|
clk <= '0';
|
||||||
|
reset <= '1';
|
||||||
|
enable <= '0';
|
||||||
|
|
||||||
|
wait for 30 ns;
|
||||||
|
assert count_out = 0;
|
||||||
|
|
||||||
|
reset <= '0';
|
||||||
|
|
||||||
|
clk <= '0';
|
||||||
|
wait for 10 ns;
|
||||||
|
clk <= '1';
|
||||||
|
wait for 10 ns;
|
||||||
|
|
||||||
|
assert count_out = 0;
|
||||||
|
|
||||||
|
enable <= '1';
|
||||||
|
direction <= '0';
|
||||||
|
|
||||||
|
clk <= '0';
|
||||||
|
wait for 10 ns;
|
||||||
|
clk <= '1';
|
||||||
|
wait for 10 ns;
|
||||||
|
|
||||||
|
assert count_out = 255;
|
||||||
|
|
||||||
|
direction <= '1';
|
||||||
|
|
||||||
|
clk <= '0';
|
||||||
|
wait for 10 ns;
|
||||||
|
clk <= '1';
|
||||||
|
wait for 10 ns;
|
||||||
|
|
||||||
|
clk <= '0';
|
||||||
|
wait for 10 ns;
|
||||||
|
clk <= '1';
|
||||||
|
wait for 10 ns;
|
||||||
|
|
||||||
|
assert count_out = 1;
|
||||||
|
|
||||||
|
wait for 30 ns;
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end test;
|
||||||
|
|
@ -1,25 +0,0 @@
|
||||||
library ieee;
|
|
||||||
use ieee.std_logic_1164.all;
|
|
||||||
|
|
||||||
entity flipflop is
|
|
||||||
port (
|
|
||||||
d : in std_logic;
|
|
||||||
e : in std_logic;
|
|
||||||
q : out std_logic;
|
|
||||||
q_n : out std_logic
|
|
||||||
);
|
|
||||||
end entity;
|
|
||||||
|
|
||||||
architecture rtl of flipflop is
|
|
||||||
signal state : std_logic;
|
|
||||||
begin
|
|
||||||
store: process(e)
|
|
||||||
begin
|
|
||||||
if rising_edge(e) then
|
|
||||||
state <= d;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
q <= state;
|
|
||||||
q_n <= not state;
|
|
||||||
end architecture;
|
|
||||||
Binary file not shown.
|
|
@ -1,44 +0,0 @@
|
||||||
library ieee;
|
|
||||||
use ieee.std_logic_1164.all;
|
|
||||||
|
|
||||||
entity flipflop_tb is
|
|
||||||
end entity;
|
|
||||||
|
|
||||||
architecture test of flipflop_tb is
|
|
||||||
signal s_d, s_e, s_q : std_logic;
|
|
||||||
begin
|
|
||||||
uut: entity work.flipflop
|
|
||||||
port map (
|
|
||||||
d => s_d,
|
|
||||||
e => s_e,
|
|
||||||
q => s_q
|
|
||||||
);
|
|
||||||
|
|
||||||
simulate: process
|
|
||||||
begin
|
|
||||||
s_d <= '0';
|
|
||||||
s_e <= '0';
|
|
||||||
|
|
||||||
wait for 100 ns;
|
|
||||||
|
|
||||||
s_e <= '1';
|
|
||||||
wait for 10 ns;
|
|
||||||
s_e <= '0';
|
|
||||||
|
|
||||||
assert s_q = '0';
|
|
||||||
|
|
||||||
wait for 50 ns;
|
|
||||||
s_d <= '1';
|
|
||||||
wait for 50 ns;
|
|
||||||
|
|
||||||
assert s_q = '0';
|
|
||||||
|
|
||||||
s_e <= '1';
|
|
||||||
wait for 10 ns;
|
|
||||||
s_e <= '0';
|
|
||||||
assert s_q = '1';
|
|
||||||
|
|
||||||
wait for 100 ns;
|
|
||||||
wait;
|
|
||||||
end process;
|
|
||||||
end architecture;
|
|
||||||
|
|
@ -11,42 +11,64 @@ Other than a text editor, the following Free Software packages have to be instal
|
||||||
|
|
||||||
\begin{savenotes}
|
\begin{savenotes}
|
||||||
\begin{description}
|
\begin{description}
|
||||||
\item[\icode{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to compile and simulate the design
|
\item[\icode{ghdl}\footnote{\url{https://github.com/ghdl/ghdl}}] to analyze, compile, and simulate the design
|
||||||
\item[\icode{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the generated waveform files
|
\item[\icode{gtkwave}\footnote{\url{http://gtkwave.sourceforge.net/}}] to view the simulation waveform files
|
||||||
\item[GNU \icode{make}] to coordinate simulating designs, compiling firmware and generating images
|
\item[\icode{yosys}\footnote{\url{http://www.clifford.at/yosys/}}] to synthesize the design
|
||||||
\item[\icode{python}] for helper scripts
|
\item[\icode{nextpnr-xilinx}\footnote{\url{https://github.com/daveshah1/nextpnr-xilinx}}] to place and route the design
|
||||||
|
\item[\icode{Project X-Ray}\footnote{\url{https://github.com/SymbiFlow/prjxray}}] for FPGA layout data and bitstream tools
|
||||||
|
\item[\icode{xc3sprog}\footnote{\url{https://sourceforge.net/projects/xc3sprog/}}] to load the bitstream onto the FPGA
|
||||||
\end{description}
|
\end{description}
|
||||||
\end{savenotes}
|
\end{savenotes}
|
||||||
|
|
||||||
\section{Creating a design}
|
\section{Creating a design}
|
||||||
|
|
||||||
A simple starting design is a D flip flop:
|
A simple starting design is an up/down counter. The following VHDL code describes the device:
|
||||||
|
|
||||||
\def\svgwidth{2cm}
|
\lstinputlisting[title=\texttt{counter.vhd}]{vhdl/counter.vhd}
|
||||||
\input{d_flip_flop.pdf_tex}
|
|
||||||
|
|
||||||
The following VHDL code describes the device:
|
|
||||||
|
|
||||||
\lstinputlisting[title=\texttt{flipflop.vhd}]{vhdl/flipflop.vhd}
|
|
||||||
|
|
||||||
In order to test this design, a test bench has to be created:
|
In order to test this design, a test bench has to be created:
|
||||||
|
|
||||||
\lstinputlisting[title=\texttt{flipflop\_tb.vhd}]{vhdl/flipflop_tb.vhd}
|
\lstinputlisting[title=\texttt{counter\_tb.vhd}]{vhdl/counter_tb.vhd}
|
||||||
|
|
||||||
\section{Simulating a design}
|
\section{Simulating a design}
|
||||||
|
|
||||||
\begin{lstlisting}[style=default,language=sh]
|
\begin{lstlisting}[style=default,language=sh]
|
||||||
# analyze the design files
|
# analyze the design files
|
||||||
ghdl -a *.vhd
|
ghdl -a --std=08 *.vhd
|
||||||
# elaborate the test bench entity
|
# elaborate the test bench entity
|
||||||
ghdl -e flipflop_tb
|
ghdl -e --std=08 counter_tb
|
||||||
# run the test bench, saving the signal trace to a GHW file
|
# run the test bench, saving the signal trace to a GHW file
|
||||||
ghdl -r flipflop_tb --wave=flipflop_tb.ghw
|
ghdl -r --std=08 counter_tb --wave=counter_tb.ghw
|
||||||
# open the trace with gtkwave
|
# open the trace with gtkwave (using the view configuration in counter_tb.gtkw)
|
||||||
gtkwave flipflop_tb.ghw
|
gtkwave counter_tb.ghw counter_tb.gtkw
|
||||||
\end{lstlisting}
|
\end{lstlisting}
|
||||||
|
|
||||||
\begin{center}
|
\begin{center}
|
||||||
\includegraphics[width=\textwidth]{flipflop_gtkwave.png}
|
\includegraphics[width=\textwidth]{counter_gtkwave.png}
|
||||||
\end{center}
|
\end{center}
|
||||||
|
|
||||||
|
\section{Synthesizing a design}
|
||||||
|
|
||||||
|
An additional Xilinx Design Constraints (XDC) file is required to assign the signals to pins on the FPGA:
|
||||||
|
|
||||||
|
\lstinputlisting[style=default,title=\texttt{counter.xdc}]{vhdl/counter.xdc}
|
||||||
|
|
||||||
|
\begin{lstlisting}[style=default,language=sh]
|
||||||
|
# synthesize with yosys
|
||||||
|
yosys -m ghdl.so -p '
|
||||||
|
ghdl --std=08 counter.vhd -e counter;
|
||||||
|
synth_xilinx -flatten;
|
||||||
|
write_json counter.json'
|
||||||
|
# place and route the design with nextpnr
|
||||||
|
nextpnr-xilinx --chipdb xc7a35tcsg324-1.bin --xdc counter.xdc --json counter.json --fasm counter.fasm
|
||||||
|
# convert the FPGA assembly to frames
|
||||||
|
fasm2frames.py --part xc7a35tcsg324-1 counter.fasm counter.frames
|
||||||
|
# convert the frames to a bitstream
|
||||||
|
xc7frames2bit --part-name xc7a35tcsg324-1 --frm-file counter.frames --output-file counter.bit
|
||||||
|
# upload the bitstream to the FPGA
|
||||||
|
xc3sprog -c nexys4 counter.bit
|
||||||
|
\end{lstlisting}
|
||||||
|
|
||||||
|
The current value of the counter is displayed in binary on the eight LEDs on the board. When switch 0 (enable) is in the high position, the counter can be advanced using button 0, with the direction set by switch 1. Button 1 resets the counter to zero.
|
||||||
|
|
||||||
\end{document}
|
\end{document}
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue