45 lines
600 B
VHDL
45 lines
600 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity flipflop_tb is
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end entity;
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architecture test of flipflop_tb is
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signal s_d, s_e, s_q : std_logic;
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begin
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uut: entity work.flipflop
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port map (
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d => s_d,
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e => s_e,
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q => s_q
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);
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simulate: process
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begin
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s_d <= '0';
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s_e <= '0';
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wait for 100 ns;
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s_e <= '1';
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wait for 10 ns;
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s_e <= '0';
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assert s_q = '0';
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wait for 50 ns;
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s_d <= '1';
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wait for 50 ns;
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assert s_q = '0';
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s_e <= '1';
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wait for 10 ns;
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s_e <= '0';
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assert s_q = '1';
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wait for 100 ns;
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wait;
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end process;
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end architecture;
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