dipl/sections/core/entities/multiplier_entity.vhd

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VHDL
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2020-03-27 12:51:39 +01:00
entity multiplier is
generic (
-- A shorter than B: faster, but wider adder required
WIDTH_A : positive;
WIDTH_B : positive
--PARALLELISM : positive
);
port (
clk : in std_logic;
run : in std_logic;
valid : out std_logic;
mul_signed : in std_logic;
a : in std_logic_vector(WIDTH_A-1 downto 0);
b : in std_logic_vector(WIDTH_B-1 downto 0);
result : out std_logic_vector(WIDTH_A+WIDTH_B-1 downto 0)
);
end multiplier;