dipl/main.toc

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\contentsline {section}{Gendererklärung}{i}{Doc-Start}% 
\contentsline {section}{Kurzfassung/Abstract}{ii}{Doc-Start}% 
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\babel@toc {ngerman}{}
\contentsline {section}{Result}{iii}{Doc-Start}% 
\babel@toc {english}{}
\contentsline {section}{\numberline {1}Task description}{1}{section.1}% 
\contentsline {subsection}{\numberline {1.1}Hardware}{1}{subsection.1.1}% 
\contentsline {section}{\numberline {2}Hardware peripherials}{2}{section.2}% 
\contentsline {subsection}{\numberline {2.1}Parallel bus}{2}{subsection.2.1}% 
\contentsline {subsubsection}{\numberline {2.1.1}Address Bus}{3}{subsubsection.2.1.1}% 
\contentsline {subsection}{\numberline {2.2}Data Bus}{3}{subsection.2.2}% 
\contentsline {subsection}{\numberline {2.3}Control Bus}{3}{subsection.2.3}% 
\contentsline {subsubsection}{\numberline {2.3.1}Master Reset}{3}{subsubsection.2.3.1}% 
\contentsline {subsubsection}{\numberline {2.3.2}Write Not}{4}{subsubsection.2.3.2}% 
\contentsline {subsubsection}{\numberline {2.3.3}Read Not}{4}{subsubsection.2.3.3}% 
\contentsline {subsubsection}{\numberline {2.3.4}Module Select 1 and 2 Not}{4}{subsubsection.2.3.4}% 
\contentsline {subsection}{\numberline {2.4}Testing and Measurement}{4}{subsection.2.4}% 
\contentsline {subsubsection}{\numberline {2.4.1}Measurements}{4}{subsubsection.2.4.1}% 
\contentsline {subsubsection}{\numberline {2.4.2}Testing}{5}{subsubsection.2.4.2}% 
\contentsline {subsection}{\numberline {2.5}Backplane}{5}{subsection.2.5}% 
\contentsline {subsubsection}{\numberline {2.5.1}Termination resistors}{6}{subsubsection.2.5.1}% 
\contentsline {subsection}{\numberline {2.6}Case}{7}{subsection.2.6}% 
\contentsline {subsection}{\numberline {2.7}Serial Console}{9}{subsection.2.7}% 
\contentsline {subsubsection}{\numberline {2.7.1}16550 UART}{9}{subsubsection.2.7.1}% 
\contentsline {subsubsection}{\numberline {2.7.2}MAX-232}{10}{subsubsection.2.7.2}% 
\contentsline {subsubsection}{\numberline {2.7.3}Schematics}{10}{subsubsection.2.7.3}% 
\contentsline {paragraph}{Element Description}{12}{figure.caption.7}% 
\contentsline {subsubsection}{\numberline {2.7.4}Demonstration Software}{14}{subsubsection.2.7.4}% 
\contentsline {paragraph}{Transmit code}{14}{figure.caption.11}% 
\contentsline {paragraph}{Echo code}{17}{figure.caption.12}% 
\contentsline {subsection}{\numberline {2.8}Audio Digital-Analog-Converter}{18}{subsection.2.8}% 
\contentsline {subsubsection}{\numberline {2.8.1}TLC 7528 Dual R2R Ladder DAC}{19}{subsubsection.2.8.1}% 
\contentsline {subsubsection}{\numberline {2.8.2}IDT7201 CMOS FIFO Buffer}{19}{subsubsection.2.8.2}% 
\contentsline {subsubsection}{\numberline {2.8.3}Theory verfication}{20}{subsubsection.2.8.3}% 
\contentsline {subsubsection}{\numberline {2.8.4}Schematics}{21}{subsubsection.2.8.4}% 
\contentsline {paragraph}{Element Description}{23}{figure.caption.17}% 
\contentsline {paragraph}{NE55 Clock Source}{24}{figure.caption.17}% 
\contentsline {subsubsection}{\numberline {2.8.5}Demonstration Software}{24}{subsubsection.2.8.5}% 
\contentsline {paragraph}{SAW Generator}{24}{subsubsection.2.8.5}% 
\contentsline {paragraph}{Sine Generator}{26}{lstnumber.4.11}% 
\contentsline {section}{\numberline {3}Addressing DACA and DACB}{28}{section.3}% 
\contentsline {subsection}{\numberline {3.1}FPGA to Hardware interface}{28}{subsection.3.1}% 
\contentsline {subsubsection}{\numberline {3.1.1}Measurement error}{31}{subsubsection.3.1.1}% 
\contentsline {section}{\numberline {4}Textadventure}{31}{section.4}% 
\contentsline {subsection}{\numberline {4.1}General Implementation details}{32}{subsection.4.1}% 
\contentsline {subsubsection}{\numberline {4.1.1}General definitions and pinout of the AVR}{32}{subsubsection.4.1.1}% 
\contentsline {subsubsection}{\numberline {4.1.2}Read and Write routines}{34}{subsubsection.4.1.2}% 
\contentsline {subsubsection}{\numberline {4.1.3}UART and DAC update polling}{34}{subsubsection.4.1.3}% 
\contentsline {subsection}{\numberline {4.2}DAC sound generation}{35}{subsection.4.2}% 
\contentsline {subsubsection}{\numberline {4.2.1}DAC modes}{35}{subsubsection.4.2.1}% 
\contentsline {subsubsection}{\numberline {4.2.2}Tones and Tracks}{40}{subsubsection.4.2.2}% 
\contentsline {subsubsection}{\numberline {4.2.3}Track switching}{44}{subsubsection.4.2.3}% 
\contentsline {subsection}{\numberline {4.3}User command interpretation}{44}{subsection.4.3}% 
\contentsline {subsubsection}{\numberline {4.3.1}Command structure and parsing}{44}{subsubsection.4.3.1}% 
\contentsline {subsubsection}{\numberline {4.3.2}Command parameters}{46}{subsubsection.4.3.2}% 
\contentsline {subsection}{\numberline {4.4}Gameplay}{47}{subsection.4.4}% 
\contentsline {subsection}{\numberline {4.5}Memory constraints}{49}{subsection.4.5}% 
\contentsline {part}{I\hspace {1em}A short introduction to VHDL}{50}{part.1}% 
\contentsline {section}{\numberline {5}Prerequisites}{50}{section.5}% 
\contentsline {section}{\numberline {6}Creating a design}{50}{section.6}% 
\contentsline {section}{\numberline {7}Simulating a design}{52}{section.7}% 
\contentsline {section}{\numberline {8}Synthesizing a design}{53}{section.8}% 
\contentsline {part}{II\hspace {1em}Meta}{54}{part.2}% 
\contentsline {section}{\numberline {9}History}{54}{section.9}% 
\contentsline {section}{\numberline {10}Tooling}{56}{section.10}% 
\contentsline {subsection}{\numberline {10.1}Vendor Tools}{56}{subsection.10.1}% 
\contentsline {subsection}{\numberline {10.2}Free Software Tools}{56}{subsection.10.2}% 
\contentsline {section}{\numberline {11}Peripherals}{57}{section.11}% 
\contentsline {subsection}{\numberline {11.1}UART}{57}{subsection.11.1}% 
\contentsline {subsection}{\numberline {11.2}DVI graphics}{57}{subsection.11.2}% 
\contentsline {subsubsection}{\numberline {11.2.1}VGA timing}{57}{subsubsection.11.2.1}% 
\contentsline {subsubsection}{\numberline {11.2.2}Text renderer}{58}{subsubsection.11.2.2}% 
\contentsline {subsubsection}{\numberline {11.2.3}TMDS encoder}{59}{subsubsection.11.2.3}% 
\contentsline {subsection}{\numberline {11.3}Ethernet}{59}{subsection.11.3}% 
\contentsline {subsection}{\numberline {11.4}WS2812 driver}{60}{subsection.11.4}% 
\contentsline {subsection}{\numberline {11.5}DRAM}{61}{subsection.11.5}% 
\contentsline {subsection}{\numberline {11.6}External Bus}{61}{subsection.11.6}% 
\contentsline {section}{\numberline {12}Testing}{62}{section.12}% 
\contentsline {subsection}{\numberline {12.1}RISC-V Compliance Tests}{62}{subsection.12.1}% 
\contentsline {part}{III\hspace {1em}The Core}{62}{part.3}% 
\contentsline {section}{\numberline {13}Overview}{63}{section.13}% 
\contentsline {section}{\numberline {14}Control}{63}{section.14}% 
\contentsline {section}{\numberline {15}Decoder}{64}{section.15}% 
\contentsline {section}{\numberline {16}Registers}{65}{section.16}% 
\contentsline {section}{\numberline {17}Arithmetic and Logic Unit (ALU)}{66}{section.17}% 
\contentsline {section}{\numberline {18}Control and Status Registers (CSR)}{66}{section.18}% 
\contentsline {section}{\numberline {19}Memory Arbiter}{67}{section.19}% 
\contentsline {section}{\numberline {20}Exception Control}{68}{section.20}% 
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\contentsline {section}{\numberline {21}Erkl"arung der Eigenst"andigkeit der Arbeit}{70}{section.21}% 
\babel@toc {english}{}
\contentsline {section}{\numberline {I\tmspace +\thickmuskip {.2777em}}List of Figures}{I}{section.1}% 
\contentsline {section}{\numberline {II\tmspace +\thickmuskip {.2777em}}List of Tables}{II}{section.2}% 
\contentsline {section}{\numberline {III\tmspace +\thickmuskip {.2777em}}Listings}{II}{section.3}% 
\contentsline {section}{Anhang}{V}{section.3}%