21 lines
484 B
VHDL
21 lines
484 B
VHDL
|
entity decoder is
|
||
|
|
port (
|
||
|
|
clk : in std_logic;
|
||
|
|
enable : in std_logic;
|
||
|
|
|
||
|
|
async_addr_rs1 : out register_addr_t;
|
||
|
|
async_addr_rs2 : out register_addr_t;
|
||
|
|
|
||
|
|
alu_muxsel_a : out mux_selector_t;
|
||
|
|
alu_muxsel_b : out mux_selector_t;
|
||
|
|
alu_muxsel_cmp2 : out mux_selector_t;
|
||
|
|
|
||
|
|
csr_muxsel_in : out mux_selector_t;
|
||
|
|
|
||
|
|
instr_info_in : in instruction_info_t;
|
||
|
|
instr_info_out : out instruction_info_t;
|
||
|
|
|
||
|
|
raise_exc : out std_logic;
|
||
|
|
exc_data : out exception_data_t
|
||
|
|
);
|
||
|
|
end decoder;
|