dipl/sections/core/entities/program_counter_entity.vhd

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VHDL
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2020-03-27 12:51:39 +01:00
entity program_counter is
port (
clk : in std_logic;
reset : in std_logic;
operation : in pc_operation_t;
pc_in : in yarm_word;
pc_out : out yarm_word
);
end program_counter;