dipl/sections/DP/fpga_interface/main.tex

\subsection{FPGA to Hardware interface}

To make the Hardware work with the FPGA's 3.3V I/O, level shifter have been
installed, and a FPGA module was built. This module maps the I/O Pins in a 
similar
way to the ATMega 2560 used in examples before. The bidirectional 5V<->3.3V
logic level converters have been obtained on amazon, and are not well
documented. Their functionality is tested and verified in both directions,
which can be seen in figures \ref{fig:3v35v} and \ref{fig:5v3v3}. The schematic
was determined through measurements with a multimeter, and the 
schematic in Figure \ref{fig:schem_lvlshift} shows similar resistor values in
the same configuration \cite{lvlshift}.

\begin{figure}[H]
\begin{tikzpicture}
	\begin{axis}[
		ylabel=Lane Voltage,
		xlabel=Time,
		grid=both,
		xmin=-1.151135531135531e-06,
		xmax=5.488864468864469e-06,
		minor tick num=5,
		width=\textwidth,
		height=0.5\textheight]

		\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200301shift3v35v.csv};
		\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200301shift3v35v.csv};
		\legend{LV-Side,HV-Side}
	\end{axis}
	\end{tikzpicture}
	\caption{3.3V to 5V conversion using the level shifter}
	\label{fig:3v35v}
\end{figure}

The in Figure \ref{fig:3v35v} shown output on the HV side corresponds with the
schematics in Figure \ref{fig:schem_lvlshift}, where one can see, that the
resistor R2 is loading the bus capacitance to a 5V high state.

\begin{figure}[H]
\begin{tikzpicture}
	\begin{axis}[
		ylabel=Lane Voltage,
		xlabel=Time,
		grid=both,
		xmin=-7.427469135802469e-07,
		xmax=3.567253086419753e-06,
		minor tick num=5,
		width=\textwidth,
		height=0.5\textheight]

		\addplot table [x=t, y=c1, col sep=comma, mark=none] {meas/20200301shift5v3v3.csv};
		\addplot table [x=t, y=c2, col sep=comma, mark=none] {meas/20200301shift5v3v3.csv};
		\legend{LV-Side,HV-Side}
	\end{axis}
	\end{tikzpicture}
	\caption{5V to 3.3V conversion using the level shifter}
	\label{fig:5v3v3}
\end{figure}

\begin{figure}[H]
	\centering
	\includegraphics[height=.4\textheight, angle=0]{pics/bidirectonal-mosfet-level-shifter.png}
	\caption{The internal schematics of the level shifter\cite{lvlshift}}
	\label{fig:schem_lvlshift}
\end{figure}

\subsubsection{Measurement error}

During an attempt to measure wether the level shifters in the final module were
working, a measurement between the LV and the HV side showed only a difference
of 0.7V. After some troubleshooting, it was found, that the Analog Discovery has
clamping diodes against the 3.3V rail shown in figure \ref{fig:ad2_diode}. These
diodes produce the 0.7V offset and prevent the parallel bus from rising to
5V when a digial I/O pin of the Analog Discovery 2 is connected to the bus.
\cite{DB3S406F0L}.

\begin{figure}[H]
	\centering
	\includegraphics[height=.4\textheight, angle=0]{pics/ad2_dio.png}
	\caption{The internal clamping diodes of the Analog Discovery 2\cite{ad2}}
	\label{fig:ad2_diode}
\end{figure}

\subsubsection{Final Module}

The final module can be seen in figure \ref{fig:fpga_mod} without the FPGA
attached. The blue modules below are the level shifters.

\begin{figure}[H]
	\centering
	\includegraphics[width=\textwidth, angle=0]{pics/fpga_int}
	\caption{The final FPGA interface module with the level shifters}
	\label{fig:fpga_mod}
\end{figure}