266 lines
7.8 KiB
Python
Executable file
266 lines
7.8 KiB
Python
Executable file
#!/usr/bin/env python3
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#
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# This file is part of LiteEth.
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#
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# Copyright (c) 2015-2022 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2020 Xiretza <xiretza@xiretza.xyz>
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# Copyright (c) 2020 Stefan Schrijvers <ximin@ximinity.net>
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# SPDX-License-Identifier: BSD-2-Clause
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import argparse
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import os
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import yaml
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from migen import *
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from litex.build.generic_platform import *
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from litex.build.xilinx.platform import XilinxPlatform
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from litex.build.lattice.platform import LatticePlatform
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.soc import SoCRegion
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from liteeth.common import *
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from liteeth import phy as liteeth_phys
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from liteeth.mac import LiteEthMAC
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from liteeth.core import LiteEthUDPIPCore
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# IOs ----------------------------------------------------------------------------------------------
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MAC_ADDRESS = 0x00183e02a914
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CLK_FREQ = int(80e6)
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_io = [
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# Clk / Rst
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("sys_clock", 0, Pins(1)),
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("sys_reset", 1, Pins(1)),
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# IP/MAC Address.
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("mac_address", 0, Pins(48)),
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("ip_address", 0, Pins(32)),
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# Interrupt
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("interrupt", 0, Pins(1)),
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# MII PHY Pads
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("mii_eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1)),
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),
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("mii_eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("mdio", Pins(1)),
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Subsignal("mdc", Pins(1)),
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Subsignal("rx_dv", Pins(1)),
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Subsignal("rx_er", Pins(1)),
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Subsignal("rx_data", Pins(4)),
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Subsignal("tx_en", Pins(1)),
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Subsignal("tx_data", Pins(4)),
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Subsignal("col", Pins(1)),
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Subsignal("crs", Pins(1))
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),
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# RMII PHY Pads
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("rmii_eth_clocks", 0,
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Subsignal("ref_clk", Pins(1))
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),
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("rmii_eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("rx_data", Pins(2)),
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Subsignal("crs_dv", Pins(1)),
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Subsignal("tx_en", Pins(1)),
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Subsignal("tx_data", Pins(2)),
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Subsignal("mdc", Pins(1)),
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Subsignal("mdio", Pins(1)),
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),
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# GMII PHY Pads
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("gmii_eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("gtx", Pins(1)),
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Subsignal("rx", Pins(1))
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),
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("gmii_eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("int_n", Pins(1)),
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Subsignal("mdio", Pins(1)),
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Subsignal("mdc", Pins(1)),
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Subsignal("rx_dv", Pins(1)),
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Subsignal("rx_er", Pins(1)),
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Subsignal("rx_data", Pins(8)),
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Subsignal("tx_en", Pins(1)),
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Subsignal("tx_er", Pins(1)),
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Subsignal("tx_data", Pins(8)),
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Subsignal("col", Pins(1)),
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Subsignal("crs", Pins(1))
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),
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# RGMII PHY Pads
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("rgmii_eth_clocks", 0,
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Subsignal("tx", Pins(1)),
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Subsignal("rx", Pins(1))
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),
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("rgmii_eth", 0,
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Subsignal("rst_n", Pins(1)),
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Subsignal("int_n", Pins(1)),
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Subsignal("mdio", Pins(1)),
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Subsignal("mdc", Pins(1)),
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Subsignal("rx_ctl", Pins(1)),
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Subsignal("rx_data", Pins(4)),
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Subsignal("tx_ctl", Pins(1)),
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Subsignal("tx_data", Pins(4))
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),
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]
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def get_udp_port_ios(name, data_width):
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return [
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(f"{name}", 0,
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Subsignal("ip_address", Pins(32)),
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# Sink.
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Subsignal("sink_valid", Pins(1)),
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Subsignal("sink_last", Pins(1)),
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Subsignal("sink_ready", Pins(1)),
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Subsignal("sink_data", Pins(data_width)),
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# Source.
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Subsignal("source_valid", Pins(1)),
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Subsignal("source_last", Pins(1)),
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Subsignal("source_ready", Pins(1)),
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Subsignal("source_data", Pins(data_width)),
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),
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]
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class PHYCore(SoCMini):
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def __init__(self, platform):
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super().__init__(platform, clk_freq=CLK_FREQ)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = CRG(
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platform.request("sys_clock"),
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platform.request("sys_reset")
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)
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# PHY --------------------------------------------------------------------------------------
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phy = liteeth_phys.LiteEthPHYMII
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ethphy = phy(
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clock_pads=platform.request("mii_eth_clocks"),
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pads=platform.request("mii_eth")
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)
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self.submodules.ethphy = ethphy
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# Timing constaints.
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# Generate timing constraints to ensure the "keep" attribute is properly set on the various
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# clocks. This also adds the constraints to the generated .xdc that can then be "imported"
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# in the project using the core.
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eth_rx_clk = getattr(ethphy, "crg", ethphy).cd_eth_rx.clk
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eth_tx_clk = getattr(ethphy, "crg", ethphy).cd_eth_tx.clk
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from liteeth.phy.model import LiteEthPHYModel
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if not isinstance(ethphy, LiteEthPHYModel):
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self.platform.add_period_constraint(
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eth_rx_clk,
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1e9/phy.rx_clk_freq
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)
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self.platform.add_period_constraint(
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eth_tx_clk,
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1e9/phy.tx_clk_freq
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)
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self.platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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eth_rx_clk,
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eth_tx_clk
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)
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class UDPCore(PHYCore):
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def __init__(self, platform):
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from liteeth.frontend.stream import LiteEthUDPStreamer
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super().__init__(platform)
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ip_address = platform.request("ip_address")
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# Core
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self.submodules.core = LiteEthUDPIPCore(
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self.ethphy,
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mac_address=MAC_ADDRESS,
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ip_address=ip_address,
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clk_freq=CLK_FREQ,
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dw=8,
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with_sys_datapath=False,
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)
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# DHCP port
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data_width = 32
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platform.add_extension(get_udp_port_ios(
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"dhcp",
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data_width=data_width,
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))
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dhcp_ios = platform.request("dhcp")
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dhcp_streamer = LiteEthUDPStreamer(
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self.core.udp,
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ip_address=dhcp_ios.ip_address,
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udp_port=67,
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data_width=data_width,
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tx_fifo_depth=64,
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rx_fifo_depth=64
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)
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self.submodules += dhcp_streamer
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self.comb += [
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# Connect UDP Sink IOs to UDP Steamer.
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dhcp_streamer.sink.valid.eq(dhcp_ios.sink_valid),
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dhcp_streamer.sink.last.eq(dhcp_ios.sink_last),
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dhcp_ios.sink_ready.eq(dhcp_streamer.sink.ready),
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dhcp_streamer.sink.data.eq(dhcp_ios.sink_data),
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# Connect UDP Streamer to UDP Source IOs.
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dhcp_ios.source_valid.eq(dhcp_streamer.source.valid),
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dhcp_ios.source_last.eq(dhcp_streamer.source.last),
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dhcp_streamer.source.ready.eq(dhcp_ios.source_ready),
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dhcp_ios.source_data.eq(dhcp_streamer.source.data),
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]
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(
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description="splink LiteEth core generator"
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)
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builder_args(parser)
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parser.set_defaults(output_dir="build")
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args = parser.parse_args()
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# Generate core --------------------------------------------------------------------------------
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platform = XilinxPlatform(
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"xc7a35ticsg324-1L",
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io=[],
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toolchain="symbiflow"
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)
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platform.add_extension(_io)
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soc = UDPCore(platform)
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builder_arguments = builder_argdict(args)
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builder_arguments["compile_gateware"] = False
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if builder_arguments["csr_csv"] is None:
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builder_arguments["csr_csv"] = os.path.join(
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builder_arguments["output_dir"],
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"csr.csv"
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)
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builder = Builder(soc, **builder_arguments)
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builder.build(build_name="liteeth_core")
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if __name__ == "__main__":
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main()
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