40 lines
1.3 KiB
VHDL
40 lines
1.3 KiB
VHDL
-- splink, ethernet-connected LED controller
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-- Copyright (C) 2022 xiretza
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Affero General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU Affero General Public License for more details.
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--
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-- You should have received a copy of the GNU Affero General Public License
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-- along with this program. If not, see <https://www.gnu.org/licenses/>.
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library ieee;
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use ieee.std_logic_1164.all;
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package util is
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function flip_endianness(val : in std_logic_vector) return std_logic_vector;
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end package;
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package body util is
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function flip_endianness(val : in std_logic_vector) return std_logic_vector is
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constant BYTES : natural := val'length / 8;
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variable ret : std_logic_vector(val'length-1 downto 0);
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begin
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assert val'length mod 8 = 0
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report "length of vector not a multiple of 8"
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severity failure;
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for i in 0 to BYTES-1 loop
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ret((BYTES-i)*8 - 1 downto (BYTES-i-1) * 8) := val((i+1)*8 - 1 downto i*8);
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end loop;
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return ret;
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end function;
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end package body;
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