23 lines
1.2 KiB
Text
23 lines
1.2 KiB
Text
SYNTH_OUTPUT_FILE = $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).eblif
|
|
|
|
$(SYNTH_WORKDIR)/%.il: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
|
|
$(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY)
|
|
$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -p 'read_verilog $(VERILOG_FILES); ghdl $(GHDL_FLAGS) $(SYNTH_ENTITY); chformal -remove; check -assert; write_rtlil $@'
|
|
|
|
$(SYNTH_WORKDIR)/%.eblif: $(SYNTH_WORKDIR)/%.il $(XDC)
|
|
cd $(SYNTH_WORKDIR) && symbiflow_synth -d artix7 -t $* -v $< -p $(PART) -x $(XDC)
|
|
|
|
$(SYNTH_WORKDIR)/%.net: $(SYNTH_WORKDIR)/%.eblif
|
|
cd $(SYNTH_WORKDIR) && symbiflow_pack -d xc7a50t_test -e $<
|
|
|
|
$(SYNTH_WORKDIR)/%.place: $(SYNTH_WORKDIR)/%.eblif $(SYNTH_WORKDIR)/%.net
|
|
cd $(SYNTH_WORKDIR) && symbiflow_place -d xc7a50t_test -e $< -n $(word 2,$^) -P $(PART)
|
|
|
|
$(SYNTH_WORKDIR)/%.route: $(SYNTH_WORKDIR)/%.eblif $(SYNTH_WORKDIR)/%.place
|
|
cd $(SYNTH_WORKDIR) && symbiflow_route -d xc7a50t_test -e $<
|
|
|
|
$(SYNTH_WORKDIR)/%.fasm: $(SYNTH_WORKDIR)/%.eblif $(SYNTH_WORKDIR)/%.route
|
|
cd $(SYNTH_WORKDIR) && symbiflow_write_fasm -d xc7a50t_test -e $<
|
|
|
|
$(SYNTH_WORKDIR)/%.bit: $(SYNTH_WORKDIR)/%.fasm
|
|
cd $(SYNTH_WORKDIR) && symbiflow_write_bitstream -d artix7 -f $< -p $(PART) -b $@
|