splink/vhdl/util.vhdl
2022-06-21 07:21:16 +02:00

39 lines
1.3 KiB
VHDL

-- splink, ethernet-connected LED controller
-- Copyright (C) 2022 xiretza
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this program. If not, see <https://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
package util is
function flip_endianness(val : in std_logic_vector) return std_logic_vector;
end package;
package body util is
function flip_endianness(val : in std_logic_vector) return std_logic_vector is
constant BYTES : natural := val'length / 8;
variable ret : std_logic_vector(val'length-1 downto 0);
begin
assert val'length mod 8 = 0
report "length of vector not a multiple of 8"
severity failure;
for i in 0 to BYTES-1 loop
ret((BYTES-i)*8 - 1 downto (BYTES-i-1) * 8) := val((i+1)*8 - 1 downto i*8);
end loop;
return ret;
end function;
end package body;