Xiretza 5f589aca37 Use wishbone interface for CPU port		2022-07-14 16:05:49 +02:00
..
ws2812_vhdl@b324850284	update ws2812 submodule	2022-06-20 10:32:36 +02:00
arty_a7.vhdl	Use wishbone interface for CPU port	2022-07-14 16:05:49 +02:00
splink.vhdl	fix: add license	2022-06-21 07:21:16 +02:00
util.vhdl	fix: add license	2022-06-21 07:21:16 +02:00