library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity splink is
	generic (
		NUM_DRIVERS : positive := 16;
		ROWS : positive := 100;
		COLS : positive := 100
	);
	port (
		clk : in std_logic;
		reset : in std_logic;

		drivers : out std_logic_vector(NUM_DRIVERS-1 downto 0)
	);
end entity;

architecture a of splink is
	signal count2: unsigned(3 downto 0);
	signal count: natural range 0 to 10000000;
begin
	process(clk)
	begin
		if rising_edge(clk) then
			if count = 10000000 then
				count <= 0;
				count2 <= count2 + 1;
			else
				count <= count + 1;
			end if;
		end if;
	end process;

	drivers <= (15 downto 4 => '0') & std_logic_vector(count2);
end architecture;