library ieee;
use ieee.std_logic_1164.all;

package util is
	function flip_endianness(val : in std_logic_vector) return std_logic_vector;
end package;

package body util is
	function flip_endianness(val : in std_logic_vector) return std_logic_vector is
		constant BYTES : natural := val'length / 8;
		variable ret : std_logic_vector(val'length-1 downto 0);
	begin
		assert val'length mod 8 = 0
			report "length of vector not a multiple of 8"
			severity failure;

		for i in 0 to BYTES-1 loop
			ret((BYTES-i)*8 - 1 downto (BYTES-i-1) * 8) := val((i+1)*8 - 1 downto i*8);
		end loop;

		return ret;
	end function;
end package body;