library ieee;
use ieee.std_logic_1164.all,
    ieee.numeric_std.all;

entity arty_a7 is
	generic (
		IS_SIMULATION : std_logic := '0'
	);
	port (
		n_reset     : in std_logic;
		buttons     : in std_logic_vector(3 downto 0);
		switches    : in std_logic_vector(3 downto 0);
		leds_simple : out std_logic_vector(3 downto 0);
		led0, led1, led2, led3 : out std_logic_vector(2 downto 0);

		-- Pmod connectors - A+D standard, B+C high-speed.
		-- Defined as inputs by default for safety, change
		-- when necessary
		pmod_a : in std_logic_vector(7 downto 0);
		pmod_b : in std_logic_vector(7 downto 0);
		pmod_c : in std_logic_vector(7 downto 0);
		pmod_d : in std_logic_vector(7 downto 0);

		clock_100mhz : in std_logic;

		uart_rx : in std_logic;
		uart_tx : out std_logic;

		mii_clk_25mhz : out std_logic;
		mii_n_reset   : out std_logic;
		mii_mdio      : inout std_logic;
		mii_mdc       : out std_logic;
		mii_rx_clk    : in std_logic;
		mii_rx_er     : in std_logic;
		mii_rx_dv     : in std_logic;
		mii_rx_data   : in std_logic_vector(3 downto 0);
		mii_tx_clk    : in std_logic;
		mii_tx_en     : out std_logic;
		mii_tx_data   : out std_logic_vector(3 downto 0);
		mii_col       : in std_logic;
		mii_crs       : in std_logic;

		ck_dig_l : inout std_logic_vector(13 downto 0);
		ck_dig_h : inout std_logic_vector(41 downto 26)
	);
end arty_a7;

architecture a of arty_a7 is
	constant NUM_DRIVERS: positive := 16;
	signal drivers: std_logic_vector(NUM_DRIVERS-1 downto 0);
begin
	--leds_simple <= (others => '0');
	led0 <= (others => '0');
	led1 <= (others => '0');
	led2 <= (others => '0');
	led3 <= (others => '0');

	uart_tx <= '0';

	mii_clk_25mhz <= '0';
	mii_n_reset <= '0';
	mii_mdio <= 'Z';
	mii_mdc <= '0';
	mii_tx_en <= '0';
	mii_tx_data <= (others => '0');

	ck_dig_l <= (others => 'Z');
	ck_dig_h <= (others => 'Z');

	leds_simple <= drivers(3 downto 0);

	splink: entity work.splink
		generic map (
			NUM_DRIVERS => NUM_DRIVERS
		)
		port map (
			clk => clock_100mhz,
			reset => not n_reset,

			drivers => drivers
		);
end architecture;