SYNTH_OUTPUT_FILE = $(SYNTH_WORKDIR)/$(YOSYS_MODULE_NAME).json

$(SYNTH_WORKDIR)/%.json: $(VHDL_FILES) $(VERILOG_FILES) | $(SYNTH_WORKDIR) $(GHDL_WORKDIR)/work-obj$(VHDL_STD).cf
	$(GHDL) make $(GHDL_FLAGS) $(SYNTH_ENTITY)
	$(YOSYS) -m $(GHDL_YOSYS_PLUGIN) -l $(SYNTH_WORKDIR)/yosys.log -p 'ghdl $(GHDL_FLAGS) -Werror -Wno-binding $(SYNTH_ENTITY); read_verilog $(VERILOG_FILES); chformal -remove; synth_xilinx -nodsp -nosrl -flatten -top $*; write_json $@'

$(SYNTH_WORKDIR)/%.fasm: $(SYNTH_WORKDIR)/%.json $(XDC)
	$(NEXTPNR) --xdc $(XDC) --json $< --chipdb /usr/share/nextpnr/xilinx-chipdb/$(PART).bin --fasm $@

$(SYNTH_WORKDIR)/%.frames: $(SYNTH_WORKDIR)/%.fasm
	$(FASM2FRAMES) --db-root $(XRAY_DATABASE) --part $(PART) $< $@

$(SYNTH_WORKDIR)/%.bit: $(SYNTH_WORKDIR)/%.frames $(XRAY_DATABASE)/$(PART)/part.yaml
	$(FRAMES2BIT) --part-file $(XRAY_DATABASE)/$(PART)/part.yaml --part-name $(PART) --frm-file $< --output-file $@